公开(公告)号：US09508623B2

公开(公告)日：2016-11-29

申请号：US14731484

申请日：2015-06-05

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L21/44 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。

公开(公告)号：US09570314B2

公开(公告)日：2017-02-14

申请号：US14881181

申请日：2015-10-13

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： William John Nelson ,  Nathapong Suthiwongsunthorn ,  Beng Yeung Ho ,  Poh Leng Wilson Ong

IPC: H01L21/3065 ,  H01L21/78 ,  H01L21/308 ,  H01L21/311 ,  H01L21/304 ,  H01L21/82 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/14 ,  H01L2223/54453 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03

Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

Abstract translation: 介绍了切割晶片的方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片在主要器件区域上由多个管芯制成并且通过晶片的第一主表面上的切割通道彼此间隔开。 在晶片的第一或第二主表面上提供膜。 薄膜至少覆盖对应于主要装置区域的区域。 该方法还包括使用该膜作为蚀刻掩模和等离子体通过晶片的暴露的半导体材料蚀刻晶片以形成间隙，以将晶片上的多个管芯分离成多个单独的管芯。

公开(公告)号：US10354934B2

公开(公告)日：2019-07-16

申请号：US15961839

申请日：2018-04-24

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L23/28 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

公开(公告)号：US09741619B2

公开(公告)日：2017-08-22

申请号：US15402192

申请日：2017-01-09

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： William John Nelson ,  Nathapong Suthiwongsunthorn ,  Beng Yeung Ho ,  Poh Leng Wilson Ong

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/304 ,  H01L21/308 ,  H01L21/311 ,  H01L23/31 ,  H01L23/00 ,  H01L21/268 ,  H01L23/544 ,  H01L23/29

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/82 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/544 ,  H01L24/14 ,  H01L2223/54453 ,  H01L2224/94 ,  H01L2224/11 ,  H01L2224/03

Abstract: Methods for dicing a wafer is presented. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies on main device regions and are spaced apart from each other by dicing channels on the first major surface of the wafer. A film is provided over first or second major surface of the wafer. The film covers at least areas corresponding to the main device regions. The method also includes using the film as an etch mask and plasma etching the wafer through exposed semiconductor material of the wafer to form gaps to separate the plurality of dies on the wafer into a plurality of individual dies.

公开(公告)号：US09978658B2

公开(公告)日：2018-05-22

申请号：US15361487

申请日：2016-11-27

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.