Method Of Synthesizing Semiconductor Nanostructures And Nanostructures Synthesized By The Method
    1.
    发明申请
    Method Of Synthesizing Semiconductor Nanostructures And Nanostructures Synthesized By The Method 审中-公开
    合成半导体纳米结构和纳米结构的方法

    公开(公告)号:US20100065810A1

    公开(公告)日:2010-03-18

    申请号:US12440233

    申请日:2007-04-05

    IPC分类号: H01L29/66 H01L21/20

    摘要: A method of synthesizing semiconductor nanostructures of at least one semiconductor material (e.g. nanowires, nanorods, nanoribbons, nanodots, quantumdots, etc.) is described which includes the steps of placing a solid catalyst particle on a substrate, placing the combination of the said substrate and the said solid catalyst in a chamber of low oxygen partial pressure, below I×10−2 mbar, adding one or more gaseous reactants comprising at least one of said semiconductor material and a suitable precursor therefor and heating the said combination to a temperature above 200° C. but below the melting point of the solid catalyst particle. Nanostructures made by the method are also claimed.

    摘要翻译: 描述了合成至少一种半导体材料(例如纳米线,纳米棒,纳米带,纳米点,量子点等)的半导体纳米结构的方法,其包括以下步骤:将固体催化剂颗粒放置在基底上,将所述基底 和所述固体催化剂在低氧分压低于I×10-2毫巴的室中,加入一种或多种包含至少一种所述半导体材料和其合适的前体的气态反应物,并将所述组合加热至高于 200℃,但低于固体催化剂颗粒的熔点。 通过该方法制造的纳米结构也被要求保护。

    Method for the cleaning and direct bonding of solids
    2.
    发明授权
    Method for the cleaning and direct bonding of solids 失效
    清洁和直接粘结固体的方法

    公开(公告)号:US5915193A

    公开(公告)日:1999-06-22

    申请号:US444035

    申请日:1995-05-18

    IPC分类号: H01L21/306 H01L21/304

    CPC分类号: H01L21/02052

    摘要: Cleaning in periodic acid (H.sub.5 IO.sub.6) aqueous solutions (HI solutions) of particular compositions removes thermally unstable hydrocarbons from the surfaces of semiconductor wafers and enables the direct bonding of semiconductor surfaces such that the bonded interface between these surfaces remains free of bubbles even after heating subsequent to bonding.

    摘要翻译: 在特定组合物的高碘酸(H5106)水溶液(HI溶液)中的清洗从半导体晶片的表面除去热不稳定的烃,并且能够直接粘合半导体表面,使得即使在加热之后这些表面之间的结合界面仍然没有气泡 粘合。

    Method for the manufacture of a pn junction with high breakdown voltage
    3.
    发明授权
    Method for the manufacture of a pn junction with high breakdown voltage 失效
    具有高击穿电压的pn结的制造方法

    公开(公告)号:US4672738A

    公开(公告)日:1987-06-16

    申请号:US776161

    申请日:1985-09-13

    摘要: A method for the manufacture of a pn junction having a high breakdown voltage at the boundary surface of a semiconductor body, utilizing a mask which has a relatively large opening for introducing a dopant therethrough into the semiconductor body, the mask having a marginal edge which extends laterally beyond the edge of the relatively large opening. In the marginal edge, the mask is provided with smaller, auxiliary openings, the openings being sized and spaced such that lesser amounts of dopant pass through the opening as the distance of the auxiliary openings from the edge of the relatively larger opening increases. Upon introducing the dopant into the semiconductor body through the mask, there is generated a doping profile which gradually approaches the boundary surface with increasing distance from the edge of the relatively large opening.

    摘要翻译: 一种用于制造在半导体本体的边界表面具有高击穿电压的pn结的方法,利用具有相对较大的开口的掩模,用于将掺杂剂引入到半导体本体中,所述掩模具有延伸的边缘 横向超过相对较大开口的边缘。 在边缘处,掩模设置有较小的辅助开口,开口的尺寸和间隔使得当辅助开口距相对较大开口的边缘的距离增加时,较少量的掺杂剂通过开口。 当通过掩模将掺杂剂引入半导体本体时,产生掺杂分布,其随着距离相对大的开口的边缘的距离增加而逐渐接近边界表面。

    Semiconductor component comprising a planar pn-junction
    4.
    发明授权
    Semiconductor component comprising a planar pn-junction 失效
    半导体元件包括平面pn结

    公开(公告)号:US4907056A

    公开(公告)日:1990-03-06

    申请号:US248150

    申请日:1988-09-23

    CPC分类号: H01L29/0615 H01L29/7424

    摘要: A semiconductor region that is inserted into a semiconductor member is provided, the latter being separated from the former by a planar pn junction including a first, more highly doped sub-region and a second, more lightly doped sub-region that is limited by a part of the pn junction that gradually approaches a boundary surface of the semiconductor member. An electrode contacts the semiconductor region and covers a part of the second sub-region and extends toward the lateral limitation of the semiconductor region to such an extent that, given the application of a voltage inhibiting the pn junction the space charge zone forming thereat has its edge lying in the boundary surface just reaching the electrode edge given a reduced breakdown voltage.

    摘要翻译: 设置插入到半导体部件中的半导体区域,后者通过平面pn结与前者分离,该平面pn结包括第一,更高掺杂的子区和第二,更轻掺杂的子区,该子区被 pn结的部分逐渐接近半导体部件的边界面。 电极接触半导体区域并且覆盖第二子区域的一部分并且朝向半导体区域的横向限制延伸到这样的程度,即,在施加抑制pn结的电压的情况下,在其上形成的空间电荷区域具有其 边缘位于刚刚到达电极边缘的边界表面,给出了降低的击穿电压。