公开(公告)号：US09024422B2

公开(公告)日：2015-05-05

申请号：US14046000

申请日：2013-10-04

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  I-Ta Tsai

IPC: H01L23/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L21/58 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.

Abstract translation: 具有嵌入式半导体元件的封装结构包括：具有活性表面的芯片，具有电极焊盘和与所述有源表面相对的无效表面; 第一绝缘保护层，其具有经由其有效表面安装在其上的芯片的芯片安装区域; 多个连接列，其设置在与所述电极焊盘对应的位置处的所述第一绝缘保护层中，并且经由焊锡凸块电连接到所述电极焊盘; 密封剂，其形成在所述第一绝缘保护层的一个表面上，所述第一绝缘保护层的芯片安装在其上，用于封装所述芯片; 以及形成在第一绝缘保护层和连接柱的另一个表面上的堆积结构。 由于包围物的抗弯曲性，防止了积层结构的翘曲。

公开(公告)号：US20130230947A1

公开(公告)日：2013-09-05

申请号：US13865220

申请日：2013-04-18

Applicant: UNIMICRON TECHNOLOGY CORPORATION

Inventor： Shih-Ping Hsu ,  I-Ta Tsai

IPC: H01L21/58

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapsulant, the warpage of the built-up structure is prevented.

Abstract translation: 具有嵌入式半导体元件的封装结构包括：具有活性表面的芯片，具有电极焊盘和与所述有源表面相对的无效表面; 第一绝缘保护层，其具有经由其有效表面安装在其上的芯片的芯片安装区域; 多个连接列，其设置在与所述电极焊盘对应的位置处的所述第一绝缘保护层中，并且经由焊锡凸块电连接到所述电极焊盘; 密封剂，其形成在所述第一绝缘保护层的一个表面上，所述第一绝缘保护层的芯片安装在其上，用于封装所述芯片; 以及形成在第一绝缘保护层和连接柱的另一个表面上的堆积结构。 由于密封剂的抗弯曲性，防止了积层结构的翘曲。

公开(公告)号：US08580608B2

公开(公告)日：2013-11-12

申请号：US13865220

申请日：2013-04-18

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  I-Ta Tsai

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.

Abstract translation: 具有嵌入式半导体元件的封装结构包括：具有活性表面的芯片，具有电极焊盘和与所述有源表面相对的无效表面; 第一绝缘保护层，其具有经由其有效表面安装在其上的芯片的芯片安装区域; 多个连接列，其设置在与所述电极焊盘对应的位置处的所述第一绝缘保护层中，并且经由焊锡凸块电连接到所述电极焊盘; 密封剂，其形成在所述第一绝缘保护层的一个表面上，所述第一绝缘保护层的芯片安装在其上，用于封装所述芯片; 以及形成在第一绝缘保护层和连接柱的另一个表面上的堆积结构。 由于包围物的抗弯曲性，防止了积层结构的翘曲。

公开(公告)号：US09232665B2

公开(公告)日：2016-01-05

申请号：US14457343

申请日：2014-08-12

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K1/00 ,  H05K3/46 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18 ,  H05K3/40 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract translation: 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。

公开(公告)号：US20140345930A1

公开(公告)日：2014-11-27

申请号：US14457338

申请日：2014-08-12

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract translation: 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。

公开(公告)号：US20140345126A1

公开(公告)日：2014-11-27

申请号：US14457348

申请日：2014-08-12

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

公开(公告)号：US20140345125A1

公开(公告)日：2014-11-27

申请号：US14457343

申请日：2014-08-12

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract translation: 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。

公开(公告)号：US20140035138A1

公开(公告)日：2014-02-06

申请号：US14046000

申请日：2013-10-04

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  I-Ta Tsai

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/80 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented.

Abstract translation: 具有嵌入式半导体元件的封装结构包括：具有活性表面的芯片，具有电极焊盘和与所述有源表面相对的无效表面; 第一绝缘保护层，其具有经由其有效表面安装在其上的芯片的芯片安装区域; 多个连接列，其设置在与所述电极焊盘对应的位置处的所述第一绝缘保护层中，并且经由焊锡凸块电连接到所述电极焊盘; 密封剂，其形成在所述第一绝缘保护层的一个表面上，所述第一绝缘保护层的芯片安装在其上，用于封装所述芯片; 以及形成在第一绝缘保护层和连接柱的另一个表面上的堆积结构。 由于包围物的抗弯曲性，防止了积层结构的翘曲。