公开(公告)号：US20140306340A1

公开(公告)日：2014-10-16

申请号：US14314242

申请日：2014-06-25

Applicant: Unimicron Technology Corporation

Inventor： Zhao-Chong Zeng

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.

Abstract translation: 具有嵌入式电子部件的封装结构包括：具有穿透其中的空腔的载体; 半导体芯片，其容纳在所述空腔中并且具有设置在其上的焊料凸块; 形成在所述载体和所述半导体芯片上以封装所述焊料凸块的电介质层; 形成在电介质层上的布线层; 形成在所述电介质层和所述布线层上的绝缘保护层; 以及形成在电介质层中的焊料材料和用于电连接布线层和焊料凸块的绝缘保护层，从而缩短半导体芯片和载体之间的信号传输路径，以避免信号损失。

公开(公告)号：US09232665B2

公开(公告)日：2016-01-05

申请号：US14457343

申请日：2014-08-12

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K1/00 ,  H05K3/46 ,  H01L23/498 ,  H01L23/50 ,  H05K1/18 ,  H05K3/40 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract translation: 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。

公开(公告)号：US09129870B2

公开(公告)日：2015-09-08

申请号：US14314242

申请日：2014-06-25

Applicant: Unimicron Technology Corporation

Inventor： Zhao-Chong Zeng

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/13 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

Abstract: A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses.

Abstract translation: 具有嵌入式电子部件的封装结构包括：具有穿透其中的空腔的载体; 半导体芯片，其容纳在所述空腔中并且具有设置在其上的焊料凸块; 形成在所述载体和所述半导体芯片上以封装所述焊料凸块的电介质层; 形成在电介质层上的布线层; 形成在所述电介质层和所述布线层上的绝缘保护层; 以及形成在电介质层中的焊料材料和用于电连接布线层和焊料凸块的绝缘保护层，从而缩短半导体芯片和载体之间的信号传输路径，以避免信号损失。

公开(公告)号：US20140345930A1

公开(公告)日：2014-11-27

申请号：US14457338

申请日：2014-08-12

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract translation: 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。

公开(公告)号：US20140345126A1

公开(公告)日：2014-11-27

申请号：US14457348

申请日：2014-08-12

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

公开(公告)号：US20140345125A1

公开(公告)日：2014-11-27

申请号：US14457343

申请日：2014-08-12

Applicant: Unimicron Technology Corporation

Inventor： Shih-Ping Hsu ,  Zhao-Chong Zeng

IPC: H05K3/46 ,  H05K3/40

CPC classification number: H05K3/4644 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/183 ,  H05K1/185 ,  H05K1/187 ,  H05K3/0097 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/0129 ,  H05K2201/10636 ,  H05K2203/1469 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00

Abstract: A packaging substrate includes: a dielectric layer unit having top and bottom surfaces; a positioning pad embedded in the bottom surface of the dielectric layer unit; at least a passive element having a plurality of electrode pads disposed on upper and lower surfaces thereof, the passive element being embedded in the dielectric layer unit and corresponding to the positioning pad; a first circuit layer disposed on the top surface of the dielectric layer unit, the first circuit layer having first conductive vias electrically connected to the electrode pads disposed on the upper surface of the passive element; and a second circuit layer disposed on the bottom surface of the dielectric layer unit, the second circuit layer having second conductive vias electrically connected to the electrode pads disposed on the lower surface of the passive element. Through the embedding of the passive element, the overall structure may have a reduced height.

Abstract translation: 包装基板包括：具有顶表面和底表面的电介质层单元; 位于所述电介质层单元的底表面中的定位焊盘; 至少一个无源元件，其具有设置在其上表面和下表面上的多个电极焊盘，所述无源元件嵌入在所述电介质层单元中并对应于所述定位焊盘; 设置在电介质层单元的顶表面上的第一电路层，第一电路层具有电连接到设置在无源元件的上表面上的电极焊盘的第一导电通孔; 以及设置在所述电介质层单元的底表面上的第二电路层，所述第二电路层具有电连接到设置在所述无源元件的下表面上的电极焊盘的第二导电通孔。 通过嵌入无源元件，整体结构可以具有减小的高度。