公开(公告)号：US20170024506A1

公开(公告)日：2017-01-26

申请号：US14807869

申请日：2015-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Ming Kuo ,  Ming-Jui Chen ,  Te-Hsien Hsieh ,  Ping-I Hsieh ,  Jing-Yi Lee ,  Yan-Chun Chen

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G06F17/5081

Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

Abstract translation: 一种用于优化集成电路布局设计的方法包括以下步骤。 获得包括具有多个金属线的金属线特征和包括具有多个孔的孔特征的第二集成电路布局设计的第一集成电路布局设计。 通过将具有孔特征的金属线特征拼接，选择孔特征的线端孔特征。 线端孔特征通过计算机系统由相邻孔之间的间隔分为单孔特征和冗余孔特征。

公开(公告)号：US20150036116A1

公开(公告)日：2015-02-05

申请号：US13957436

申请日：2013-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Hsien Hsieh ,  Shih-Ming Kuo ,  Ming-Jui Chen ,  Cheng-Te Wang ,  Jing-Yi Lee

IPC: G03F7/20

CPC classification number: G03F7/70308 ,  G03F7/7025

Abstract: An aperture is configured to be disposed between an illumination source and a semiconductor substrate in a photolithography system. The aperture includes a light-transmission portion with a non-planar thickness profile to compensate the discrepancy of wave-fronts of the light beams of different orders.

Abstract translation: 孔被配置为在光刻系统中设置在照明源和半导体衬底之间。 孔径包括具有非平面厚度轮廓的光透射部分，以补偿不同阶数的光束的波前差异。

公开(公告)号：US09747404B2

公开(公告)日：2017-08-29

申请号：US14807869

申请日：2015-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Ming Kuo ,  Ming-Jui Chen ,  Te-Hsien Hsieh ,  Ping-I Hsieh ,  Jing-Yi Lee ,  Yan-Chun Chen

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G06F17/5081

Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.

公开(公告)号：US08745547B1

公开(公告)日：2014-06-03

申请号：US13940096

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Ming Kuo ,  Ming-Jui Chen ,  Te-Hsien Hsieh ,  Cheng-Te Wang ,  Jing-Yi Lee

IPC: G06F17/50

CPC classification number: G03F1/70

Abstract: A method for making a photomask layout is disclosed. A graphic data of a photomask is provided. A first correction step is performed to the graphic data. A first verification step is performed to all of the graphic data which has been subjected to the first correction step, wherein at least one failed pattern not passing the first verification step is found. A second correction step is performed to the at least one failed pattern, so as to obtain at least one modified pattern. A second verification step is performed only to at least one buffer region covering the at least one modified pattern, wherein the buffer region has an area less than a whole area of the photomask. Besides, each of the first correction step, the first verification step, the second correction step and the second verification step is executed by a computer.

Abstract translation: 公开了一种制造光掩模布局的方法。 提供光掩模的图形数据。 对图形数据执行第一校正步骤。 对已经经过第一校正步骤的所有图形数据执行第一验证步骤，其中找到不通过第一验证步骤的至少一个故障模式。 对所述至少一个故障模式执行第二校正步骤，以便获得至少一个修改的模式。 第二验证步骤仅对覆盖至少一个修改图案的至少一个缓冲区域执行，其中缓冲区域具有小于光掩模的整个区域的面积。 此外，第一校正步骤，第一校验步骤，第二校正步骤和第二校验步骤中的每一个由计算机执行。