公开(公告)号：US12040396B2

公开(公告)日：2024-07-16

申请号：US18116826

申请日：2023-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26533 ,  H01L21/2822 ,  H01L29/0653 ,  H01L29/66681 ,  H01L21/28211

Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

公开(公告)号：US20240213247A1

公开(公告)日：2024-06-27

申请号：US18107983

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Lin ,  Zen-Jay Tsai ,  Chun-Hsien Lin

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a first region and a second region, forming a first gate dielectric layer on the first region, forming a second gate dielectric layer on the second region, and forming a first gate structure on the first gate dielectric layer and the second gate dielectric layer. Preferably, the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

公开(公告)号：US20230207692A1

公开(公告)日：2023-06-29

申请号：US18116826

申请日：2023-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/7816 ,  H01L21/26533 ,  H01L29/0653 ,  H01L29/66681 ,  H01L21/2822 ,  H01L21/28211

Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

公开(公告)号：US20210104554A1

公开(公告)日：2021-04-08

申请号：US16699474

申请日：2019-11-29

Applicant: United Microelectronics Corp.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Chung-Liang Chu ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

公开(公告)号：US11721702B2

公开(公告)日：2023-08-08

申请号：US17844067

申请日：2022-06-20

Applicant: United Microelectronics Corp.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Chung-Liang Chu ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L27/12 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.

公开(公告)号：US20220140139A1

公开(公告)日：2022-05-05

申请号：US17109153

申请日：2020-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265

Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

公开(公告)号：US20240322036A1

公开(公告)日：2024-09-26

申请号：US18736560

申请日：2024-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26533 ,  H01L21/2822 ,  H01L29/0653 ,  H01L29/66681 ,  H01L21/28211

Abstract: A semiconductor device includes a substrate, a buried oxide layer in the substrate and near a surface of the substrate, a gate dielectric layer on the substrate and covering the buried oxide layer, a gate structure disposed on the gate dielectric layer and overlapping the buried oxide layer, a source region and a drift region in the substrate and respectively at two sides of the gate structure, wherein the drift region partially covers a lower edge of the buried oxide layer and exposes a side edge of the buried oxide layer, and a drain region in the drift region.

公开(公告)号：US11869953B2

公开(公告)日：2024-01-09

申请号：US17943654

申请日：2022-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/06

CPC classification number: H01L29/42364 ,  H01L21/28238 ,  H01L29/0653

Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.

公开(公告)号：US11626515B2

公开(公告)日：2023-04-11

申请号：US17109153

申请日：2020-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H01L27/088

Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

公开(公告)号：US11476343B2

公开(公告)日：2022-10-18

申请号：US17213868

申请日：2021-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Yao Huang ,  Yu-Ruei Chen ,  Zen-Jay Tsai ,  Yu-Hsiang Lin

IPC: H01L21/70 ,  H01L29/423 ,  H01L21/28 ,  H01L29/06

Abstract: A high-voltage transistor device includes a semiconductor substrate, an isolation structure, a gate dielectric layer, a gate, a source region and a drain region. The semiconductor substrate has a plurality of grooves extending downward from a surface of the semiconductor substrate to form a sawtooth sectional profile. The isolation structure is disposed on the outside of the plurality of grooves, and extends from the surface downwards into the semiconductor substrate to define a high-voltage area. The gate dielectric layer is disposed on the high-voltage area and partially filled in the plurality of grooves. The gate is disposed on the gate dielectric layer. The source region and the drain region are respectively disposed in the semiconductor substrate and isolated from each other.