公开(公告)号：US08664055B2

公开(公告)日：2014-03-04

申请号：US13693009

申请日：2012-12-03

Applicant: United Microelectronics Corporation

Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC: H01L21/8238

CPC classification number: H01L29/78 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7833

Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.

Abstract translation: 鳍状场效应晶体管结构包括衬底，鳍状沟道和高k金属栅极。 高k金属栅极形成在基板和鳍状通道上。 制造鳍式场效应晶体管结构的工艺包括以下步骤。 首先，在基板和散热片通道的表面上形成多晶硅伪栅极结构。 通过使用多晶硅伪栅极结构作为掩模，在鳍式沟道中形成源/漏区。 在去除多晶硅伪栅极结构之后，依次形成高k电介质层和金属栅极层。 然后，在具有金属栅极层的基板上进行平坦化处理，直到第一介电层露出为止，从而产生高k金属栅极。

公开(公告)号：US09263282B2

公开(公告)日：2016-02-16

申请号：US13916584

申请日：2013-06-13

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/31 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/306 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Abstract translation: 制造半导体图案的方法包括以下步骤：首先，提供基板，并且至少具有第一半导体图案和至少第二半导体图案，其中第一半导体图案的线宽与第一半导体图案的线宽相同 第二半导体图案。 然后，在第一半导体图案的表面上形成阻挡图案，露出第二半导体图案。 然后，使第二半导体图案的表面部分反应形成牺牲结构层。 然后，去除阻挡图案和牺牲结构层，并且使第二半导体图案的线宽缩小到小于第一半导体图案的线宽。 可以进一步提供具有线宽的第三半导体图案。

公开(公告)号：US20140370701A1

公开(公告)日：2014-12-18

申请号：US13916584

申请日：2013-06-13

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/28 ,  H01L21/306

CPC classification number: H01L21/306 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Abstract translation: 制造半导体图案的方法包括以下步骤：首先，提供基板，并且至少具有第一半导体图案和至少第二半导体图案，其中第一半导体图案的线宽与第一半导体图案的线宽相同 第二半导体图案。 然后，在第一半导体图案的表面上形成阻挡图案，露出第二半导体图案。 然后，使第二半导体图案的表面部分反应形成牺牲结构层。 然后，去除阻挡图案和牺牲结构层，并且使第二半导体图案的线宽缩小到小于第一半导体图案的线宽。 可以进一步提供具有线宽的第三半导体图案。

公开(公告)号：US08847325B2

公开(公告)日：2014-09-30

申请号：US13689720

申请日：2012-11-29

Applicant: United Microelectronics Corporation

Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC: H01L21/70 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7833

Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.

Abstract translation: 鳍状场效应晶体管结构包括衬底，鳍状沟道，源极/漏极区域，高k金属栅极和多个狭槽接触结构。 翅片通道形成在基板上。 源极/漏极区域形成在鳍状沟道中。 形成在基板和鳍状沟道上的高k金属栅包括高k电介质层和金属栅极层，其中高k电介质层布置在金属栅极层和鳍状沟之间。 槽接触结构设置在金属门的两侧。

公开(公告)号：US20140035070A1

公开(公告)日：2014-02-06

申请号：US14045798

申请日：2013-10-04

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Tsuo-Wen Lu ,  Tzung-Ying Lee ,  Jei-Ming Chen ,  Chun-Wei Hsu ,  Yu-Min Lin ,  Chia-Lung Chang ,  Chin-Cheng Chien ,  Shu-Yen Chan

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833

Abstract: A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure.

Abstract translation: 提供了一种MOS晶体管，其包括硅衬底，设置在硅衬底上的第一栅极结构和第二栅极结构。 第一栅极结构和第二栅极结构各自包括设置在硅衬底上的高k电介质层，设置在高k电介质层上的阻挡层和设置在阻挡层上并与阻挡层接触的功函数层。 MOS晶体管还包括电介质材料间隔物。 电介质材料间隔物设置在第一栅极结构和第二栅极结构中的每一个的势垒层上并且围绕第一栅极结构和第二栅极结构中的每一个的功函数层。