公开(公告)号：US20140073109A1

公开(公告)日：2014-03-13

申请号：US14071664

申请日：2013-11-05

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Liang-An Huang ,  Yu-Chun Huang ,  Chin-Fu Lin ,  Yu-Ciao Lin ,  Yu-Chieh Lin ,  Hsin-Liang Liu ,  Chun-Hung Cheng ,  Yuan-Cheng Yang ,  Yau-Kae Sheu

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76232

Abstract: A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Abstract translation: 浅沟槽隔离结构的制造方法包括以下步骤。 首先，提供衬底，其中在衬底中限定高电压器件区域。 然后，执行第一蚀刻工艺以部分地去除衬底，从而在高压器件区域中形成初步浅沟槽。 然后，进行第二蚀刻处理以进一步去除对应于初步浅沟槽的衬底，从而在高电压器件区域中形成第一浅沟槽。 之后，在第一浅沟槽中填充电介质材料，从而形成第一浅沟槽隔离结构。

公开(公告)号：US20140370701A1

公开(公告)日：2014-12-18

申请号：US13916584

申请日：2013-06-13

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/28 ,  H01L21/306

CPC classification number: H01L21/306 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Abstract translation: 制造半导体图案的方法包括以下步骤：首先，提供基板，并且至少具有第一半导体图案和至少第二半导体图案，其中第一半导体图案的线宽与第一半导体图案的线宽相同 第二半导体图案。 然后，在第一半导体图案的表面上形成阻挡图案，露出第二半导体图案。 然后，使第二半导体图案的表面部分反应形成牺牲结构层。 然后，去除阻挡图案和牺牲结构层，并且使第二半导体图案的线宽缩小到小于第一半导体图案的线宽。 可以进一步提供具有线宽的第三半导体图案。

公开(公告)号：US08847325B2

公开(公告)日：2014-09-30

申请号：US13689720

申请日：2012-11-29

Applicant: United Microelectronics Corporation

Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC: H01L21/70 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7833

Abstract: A fin field-effect transistor structure comprises a substrate, a fin channel, a source/drain region, a high-k metal gate and a plurality of slot contact structures. The fin channel is formed on the substrate. The source/drain region is formed in the fin channel. The high-k metal gate formed on the substrate and the fin channel comprises a high-k dielectric layer and a metal gate layer, wherein the high-k dielectric layer is arranged between the metal gate layer and the fin channel. The slot contact structures are disposed at both sides of the metal gate.

Abstract translation: 鳍状场效应晶体管结构包括衬底，鳍状沟道，源极/漏极区域，高k金属栅极和多个狭槽接触结构。 翅片通道形成在基板上。 源极/漏极区域形成在鳍状沟道中。 形成在基板和鳍状沟道上的高k金属栅包括高k电介质层和金属栅极层，其中高k电介质层布置在金属栅极层和鳍状沟之间。 槽接触结构设置在金属门的两侧。

公开(公告)号：US08815703B2

公开(公告)日：2014-08-26

申请号：US14071664

申请日：2013-11-05

Applicant: United Microelectronics Corporation

Inventor： Liang-An Huang ,  Yu-Chun Huang ,  Chin-Fu Lin ,  Yu-Ciao Lin ,  Yu-Chieh Lin ,  Hsin-Liang Liu ,  Chun-Hung Cheng ,  Yuan-Cheng Yang ,  Yau-Kae Sheu

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76232

Abstract: A fabricating method of a shallow trench isolation structure includes the following steps. Firstly, a substrate is provided, wherein a high voltage device area is defined in the substrate. Then, a first etching process is performed to partially remove the substrate, thereby forming a preliminary shallow trench in the high voltage device area. Then, a second etching process is performed to further remove the substrate corresponding to the preliminary shallow trench, thereby forming a first shallow trench in the high voltage device area. Afterwards, a dielectric material is filled in the first shallow trench, thereby forming a first shallow trench isolation structure.

Abstract translation: 浅沟槽隔离结构的制造方法包括以下步骤。 首先，提供衬底，其中在衬底中限定高电压器件区域。 然后，执行第一蚀刻工艺以部分地去除衬底，从而在高压器件区域中形成初步浅沟槽。 然后，进行第二蚀刻处理以进一步去除对应于初步浅沟槽的衬底，从而在高电压器件区域中形成第一浅沟槽。 之后，在第一浅沟槽中填充电介质材料，从而形成第一浅沟槽隔离结构。

公开(公告)号：US20130330919A1

公开(公告)日：2013-12-12

申请号：US13960812

申请日：2013-08-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun-Hsien LIN ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

公开(公告)号：US09263282B2

公开(公告)日：2016-02-16

申请号：US13916584

申请日：2013-06-13

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC: H01L21/31 ,  H01L21/306 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/306 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Abstract translation: 制造半导体图案的方法包括以下步骤：首先，提供基板，并且至少具有第一半导体图案和至少第二半导体图案，其中第一半导体图案的线宽与第一半导体图案的线宽相同 第二半导体图案。 然后，在第一半导体图案的表面上形成阻挡图案，露出第二半导体图案。 然后，使第二半导体图案的表面部分反应形成牺牲结构层。 然后，去除阻挡图案和牺牲结构层，并且使第二半导体图案的线宽缩小到小于第一半导体图案的线宽。 可以进一步提供具有线宽的第三半导体图案。

公开(公告)号：US09190292B2

公开(公告)日：2015-11-17

申请号：US14722174

申请日：2015-05-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun-Hsien Lin ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/40

CPC classification number: H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

公开(公告)号：US09087782B2

公开(公告)日：2015-07-21

申请号：US13960812

申请日：2013-08-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Kun-Hsien Lin ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

Abstract translation: 提供蚀刻停止层的制造工艺。 制造方法包括提供基板的步骤; 在所述衬底上形成栅极叠层结构，其中所述栅极堆叠结构至少包括虚设多晶硅层和阻挡层; 去除所述虚设多晶硅层以限定沟槽并暴露所述阻挡层的表面; 在阻挡层的表面和沟槽的内壁上形成修复层; 以及在修复层上形成蚀刻停止层。 此外，具有蚀刻停止层的栅极堆叠结构的制造工艺还包括在沟槽内的蚀刻停止层上形成N型功函数金属层，并且在N型功函数金属上形成栅极层 沟内的层。

公开(公告)号：US08664055B2

公开(公告)日：2014-03-04

申请号：US13693009

申请日：2012-12-03

Applicant: United Microelectronics Corporation

Inventor： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chin-Cheng Chien

IPC: H01L21/8238

CPC classification number: H01L29/78 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7833

Abstract: A fin field-effect transistor structure includes a substrate, a fin channel and a high-k metal gate. The high-k metal gate is formed on the substrate and the fin channel. A process of manufacturing the fin field-effect transistor structure includes the following steps. Firstly, a polysilicon pseudo gate structure is formed on the substrate and a surface of the fin channel. By using the polysilicon pseudo gate structure as a mask, a source/drain region is formed in the fin channel. After the polysilicon pseudo gate structure is removed, a high-k dielectric layer and a metal gate layer are successively formed. Afterwards, a planarization process is performed on the substrate having the metal gate layer until the first dielectric layer is exposed, so that a high-k metal gate is produced.

Abstract translation: 鳍状场效应晶体管结构包括衬底，鳍状沟道和高k金属栅极。 高k金属栅极形成在基板和鳍状通道上。 制造鳍式场效应晶体管结构的工艺包括以下步骤。 首先，在基板和散热片通道的表面上形成多晶硅伪栅极结构。 通过使用多晶硅伪栅极结构作为掩模，在鳍式沟道中形成源/漏区。 在去除多晶硅伪栅极结构之后，依次形成高k电介质层和金属栅极层。 然后，在具有金属栅极层的基板上进行平坦化处理，直到第一介电层露出为止，从而产生高k金属栅极。