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1.发明授权公开(公告)号：US11549913B2
公开(公告)日：2023-01-10
申请号：US15976585
申请日：2018-05-10
摘要： Methods of forming a shear-mode chemical/physical sensor for liquid environment sensing on V-shaped grooves of a [100] crystal orientation Si layer and the resulting devices are provided. Embodiments include forming a set of V-shaped grooves in a [100] Si layer over a substrate; forming an acoustic resonator over and along the V-shaped grooves, the acoustic resonator including a first metal layer, a thin-film piezoelectric layer, and a second metal layer in an IDT pattern or a sheet; and forming at least one functional layer along a slope of the acoustic resonator.
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公开(公告)号：US12037239B2
公开(公告)日：2024-07-16
申请号：US17206116
申请日：2021-03-18
IPC分类号： B81C1/00 , B06B1/06 , B81B3/00 , H10N30/06 , H10N30/074 , H10N30/093 , H10N30/87 , H10N39/00 , H10N30/853 , H10N30/88
CPC分类号： B81C1/00246 , B06B1/06 , B81B3/0021 , H10N30/06 , H10N30/074 , H10N30/875 , H10N39/00 , B81B2201/0271 , B81B2201/032 , B81B2207/015 , B81B2207/096 , B81B2207/115 , B81C2201/0105 , B81C2203/0735 , B81C2203/0771 , H10N30/093 , H10N30/853 , H10N30/883
摘要： A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.
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3.发明授权公开(公告)号：US10892730B2
公开(公告)日：2021-01-12
申请号：US15993155
申请日：2018-05-30
IPC分类号： H03H9/02 , H03H3/02 , H01L41/053 , H03H9/56 , H03H9/13 , H03H9/205 , H01L41/047 , H01L41/23 , H01L41/187 , H01L41/193
摘要： A BAW resonator/filter with a monolithic TFE package that defines an acoustic BC and suppresses resonances from the low-Q piezoelectric area of the resonator and resulting devices are provided. Embodiments include a BAW resonator over a dielectric layer, the BAW resonator including a first metal layer, a thin-film piezoelectric layer, and a second metal layer; a first cavity in the dielectric layer under the first metal layer and a second cavity over the first cavity on the second metal layer; and a pair of TFE anchors on the second metal layer, each TFE anchor adjacent to and on an opposite side of the second cavity and extending beyond the first metal layer.
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4.发明申请公开(公告)号：US20200152697A1
公开(公告)日：2020-05-14
申请号：US16183822
申请日：2018-11-08
IPC分类号： H01L27/20 , H01L41/04 , H01L41/047 , H01L41/053 , H01L41/08 , H01L41/23 , H01L41/29 , H01L41/332 , B06B1/02 , B06B1/06
摘要： According to various embodiments, a PMUT device may include a wafer, an active layer including a piezoelectric stack, an intermediate layer having a cavity therein where the intermediate layer is disposed between the wafer and the active layer such that the cavity is adjoining the piezoelectric stack. A via may be formed through the active layer and the intermediate layer to the wafer. A metallic layer may be disposed over the active layer and over surfaces of the via. The intermediate layer may include an interposing material surrounding the cavity, and may further include a sacrificial material surrounding the via. The sacrificial material may be different from the interposing material. The metallic layer may include a first member at least substantially overlapping the piezoelectric stack, a second member extending from the first member to the cavity, and a third member extending into the active layer to contact an electrode therein.
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公开(公告)号：US11329098B2
公开(公告)日：2022-05-10
申请号：US16183822
申请日：2018-11-08
IPC分类号： H01L27/20 , H01L41/04 , B06B1/06 , H01L41/047 , H01L41/053 , H01L41/23 , H01L41/29 , H01L41/332 , B06B1/02 , H01L41/08 , B81B3/00 , B81C1/00 , B81B7/00
摘要： According to various embodiments, a PMUT device may include a wafer, an active layer including a piezoelectric stack, an intermediate layer having a cavity therein where the intermediate layer is disposed between the wafer and the active layer such that the cavity is adjoining the piezoelectric stack. A via may be formed through the active layer and the intermediate layer to the wafer. A metallic layer may be disposed over the active layer and over surfaces of the via. The intermediate layer may include an interposing material surrounding the cavity, and may further include a sacrificial material surrounding the via. The sacrificial material may be different from the interposing material. The metallic layer may include a first member at least substantially overlapping the piezoelectric stack, a second member extending from the first member to the cavity, and a third member extending into the active layer to contact an electrode therein.
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公开(公告)号：US10988376B2
公开(公告)日：2021-04-27
申请号：US15840881
申请日：2017-12-13
IPC分类号： B81C1/00 , B81B3/00 , B06B1/06 , H01L41/047 , H01L41/29 , H01L41/314 , H01L27/20 , H01L41/053 , H01L41/39 , H01L41/187
摘要： A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.
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