公开(公告)号：US20130181261A1

公开(公告)日：2013-07-18

申请号：US13348894

申请日：2012-01-12

申请人： VEERARAGHAVAN S. BASKER ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： VEERARAGHAVAN S. BASKER ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/20

CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/78

摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

摘要翻译： 公开了无边界接触结构或部分无边界接触结构和制造方法。 该方法包括在栅极结构内形成栅极结构和由间隔物限定的空间。 该方法还包括在该空间中，在栅极结构上和半导体材料上覆盖密封材料。 该方法还包括从栅极结构和半导体材料上方移除密封材料，将密封材料留在空间内。 该方法还包括在栅极结构上形成层间电介质材料。 该方法进一步包括图案化层间电介质材料以形成暴露半导体材料和栅极结构的一部分的开口。 该方法还包括在形成在层间电介质材料中的开口中形成接触。

公开(公告)号：US20130313649A1

公开(公告)日：2013-11-28

申请号：US13524131

申请日：2012-06-15

申请人： VEERARAGHAVAN S. BASKER ,  EFFENDI LEOBANDUNG ,  TENKO YAMASHITA ,  CHUN-CHEN YEH

发明人： VEERARAGHAVAN S. BASKER ,  EFFENDI LEOBANDUNG ,  TENKO YAMASHITA ,  CHUN-CHEN YEH

IPC分类号： H01L27/088

CPC分类号： H01L21/845 ,  H01L27/1211

摘要： Multigate transistor devices and methods of their fabrication are disclosed. One such device includes a plurality of semiconductor fins that have source and drain regions and a gate structure overlaying the fins. The device further includes a dielectric layer that is beneath the gate structure and the fins. Here, the dielectric layer includes first dielectric regions that are disposed beneath the fins and second dielectric regions that are disposed between the fins. In addition, the first dielectric regions have a density that is greater than a density of the second dielectric regions.

摘要翻译： 公开了多晶体管器件及其制造方法。 一种这样的装置包括具有源极和漏极区域以及覆盖鳍片的栅极结构的多个半导体鳍片。 该器件还包括在栅极结构和鳍片之下的介电层。 这里，电介质层包括设置在散热片之下的第一介电区域和设置在散热片之间的第二电介质区域。 此外，第一电介质区域的密度大于第二电介质区域的密度。

公开(公告)号：US20110108920A1

公开(公告)日：2011-05-12

申请号：US12614906

申请日：2009-11-09

申请人： VEERARAGHAVAN S. BASKER ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

发明人： VEERARAGHAVAN S. BASKER ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

IPC分类号： H01L29/49 ,  H01L21/84

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

摘要翻译： 用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。 施主材料外延地沉积在鳍结构的暴露的侧壁上。 施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。 施主材料被去除，并且从翅片结构形成场效应晶体管。

公开(公告)号：US20130316513A1

公开(公告)日：2013-11-28

申请号：US13478976

申请日：2012-05-23

申请人： VEERARAGHAVAN S. BASKER ,  EFFENDI LEOBANDUNG ,  TENKO YAMASHITA ,  CHUN-CHEN YEH

发明人： VEERARAGHAVAN S. BASKER ,  EFFENDI LEOBANDUNG ,  TENKO YAMASHITA ,  CHUN-CHEN YEH

IPC分类号： H01L21/762

CPC分类号： H01L21/845 ,  H01L27/1211

摘要： Multigate transistor devices and methods of their fabrication are disclosed. In one method, a substrate including a semiconductor upper layer and a lower layer beneath the upper layer is provided. The lower layer has a rate of transformation into a dielectric that is higher than a rate of transformation into a dielectric of the upper layer when the upper and lower layers are subjected to dielectric transformation conditions. Fins are formed in the upper layer, and the lower layer beneath the fins is transformed into a dielectric material to electrically isolate the fins. In addition, a gate structure is formed over the fins to complete the multigate transistor device.

摘要翻译： 公开了多晶体管器件及其制造方法。 在一种方法中，提供了包括上层下面的半导体上层和下层的衬底。 当上层和下层经历介电转变条件时，下层具有比电介质的转变速率高于上层电介质的转变速率。 翅片形成在上层中，翅片下方的下层转变成电介质材料以电隔离翅片。 此外，在鳍片之上形成栅极结构以完成多栅极晶体管器件。