公开(公告)号：US09460024B2

公开(公告)日：2016-10-04

申请号：US13906004

申请日：2013-05-30

Applicant: VMware, Inc.

Inventor： Bhavesh Davda ,  Benjamin Charles Serebrin

IPC: G06F13/28 ,  G06F12/10 ,  G06F12/14

CPC classification number: G06F13/28 ,  G06F9/45533 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/151 ,  G06F2212/602 ,  G06F2212/654

Abstract: Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing received data in a first memory. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to store first received data in a first buffer indexed by a first descriptor in the ring of descriptors and before second received data to be stored in the first memory is received, the first address translation being associated with a second DMA operation for storing the second received data in the first memory.

Abstract translation: 公开了涉及地址转换的直接存储器访问操作的延迟减少。 本文公开的执行直接存储器访问（DMA）操作的示例方法包括初始化描述符环，描述符以索引各个缓冲器，用于将接收到的数据存储在第一存储器中。 这样的示例性方法还包括在执行第一DMA操作之后执行在执行第一DMA操作之后执行在描述符环中与第二描述符相关联的第一地址转换的预取，以将第一接收数据存储在由第一描述符索引的第一缓冲器中 接收到要存储在第一存储器中的第二接收数据之前和之后的第二地址转换与第二DMA操作相关联，以将第二接收数据存储在第一存储器中。

公开(公告)号：US09317444B2

公开(公告)日：2016-04-19

申请号：US13906010

申请日：2013-05-30

Applicant: VMware, Inc.

Inventor： Bhavesh Davda ,  Benjamin Charles Serebrin

IPC: G06F13/28 ,  G06F12/10

CPC classification number: G06F13/28 ,  G06F9/45533 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/151 ,  G06F2212/602 ,  G06F2212/654

Abstract: Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing, in a first memory, data to be transmitted. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to retrieve, for transmission, first data from a first buffer indexed by a first descriptor in the ring of descriptors and before second data is determined to be ready for transmission, the first address translation being associated with a second DMA operation for retrieving the second data from the first memory.

Abstract translation: 公开了涉及地址转换的直接存储器访问操作的延迟减少。 用于执行直接存储器访问（DMA）操作的示例性方法包括初始化描述符环，描述符以索引各个缓冲器，用于在第一存储器中存储要发送的数据。 这样的示例方法还包括在执行第一DMA操作之后执行在执行第一DMA操作之后执行在描述符环中与第二描述符相关联的第一地址转换的预取，以从第一描述符索引的第一缓冲区中检索第一数据， 描述符的环和第二数据之前被确定为准备传输，第一地址转换与用于从第一存储器检索第二数据的第二DMA操作相关联。

公开(公告)号：US20140281055A1

公开(公告)日：2014-09-18

申请号：US13906004

申请日：2013-05-30

Applicant: VMWare, Inc.

Inventor： Bhavesh Davda ,  Benjamin Charles Serebrin

IPC: G06F12/10

CPC classification number: G06F13/28 ,  G06F9/45533 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/151 ,  G06F2212/602 ,  G06F2212/654

Abstract: Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing received data in a first memory. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to store first received data in a first buffer indexed by a first descriptor in the ring of descriptors and before second received data to be stored in the first memory is received, the first address translation being associated with a second DMA operation for storing the second received data in the first memory.

Abstract translation: 公开了涉及地址转换的直接存储器访问操作的延迟减少。 本文公开的执行直接存储器访问（DMA）操作的示例方法包括初始化描述符环，描述符以索引各个缓冲器，用于将接收到的数据存储在第一存储器中。 这样的示例性方法还包括在执行第一DMA操作之后执行在执行第一DMA操作之后执行在描述符环中与第二描述符相关联的第一地址转换的预取，以将第一接收数据存储在由第一描述符索引的第一缓冲器中 接收到要存储在第一存储器中的第二接收数据之前和之后的第二地址转换与第二DMA操作相关联，以将第二接收数据存储在第一存储器中。

公开(公告)号：US20150254087A1

公开(公告)日：2015-09-10

申请号：US14721461

申请日：2015-05-26

Applicant: VMware, Inc.

Inventor： Benjamin Charles Serebrin ,  Daniel Michael Hecht

IPC: G06F9/455 ,  G06F11/34

CPC classification number: G06F9/45533 ,  G06F9/455 ,  G06F9/45558 ,  G06F11/3466 ,  G06F2009/45591 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/88

Abstract: Methods, apparatus, and articles of manufacture to virtualize performance counters are disclosed. An example method includes dividing performance events to be counted into a plurality of classes; assigning a first virtual performance counter of a virtual machine to a first performance event type in a first one of the classes; assigning a second virtual performance counter of the virtual machine to a second performance event type in a second one of the classes different from the first class; incrementing the first virtual performance counter in response to a first occurrence of the first performance event type during direct execution of guest instructions by the virtual machine; and not incrementing the first virtual performance counter in response to a second occurrence of the first performance event type during execution of emulated instructions by a hypervisor on behalf of the virtual machine.

Abstract translation: 公开了虚拟化性能计数器的方法，装置和制造。 示例性方法包括将要计数的性能事件划分为多个类; 在第一类中将虚拟机的第一虚拟性能计数器分配给第一性能事件类型; 将所述虚拟机的第二虚拟性能计数器分配到与所述第一类不同的第二类中的第二性能事件类型; 在虚拟机的直接执行访客指令期间响应于第一性能事件类型的第一次出现来增加第一虚拟性能计数器; 并且在虚拟机管理程序代表虚拟机执行仿真指令期间，不响应于第一执行事件类型的第二次出现来递增第一虚拟性能计数器。

公开(公告)号：US20140281056A1

公开(公告)日：2014-09-18

申请号：US13906010

申请日：2013-05-30

Applicant: VMware, Inc.

Inventor： Bhavesh Davda ,  Benjamin Charles Serebrin

IPC: G06F13/28

CPC classification number: G06F13/28 ,  G06F9/45533 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/151 ,  G06F2212/602 ,  G06F2212/654

Abstract: Latency reduction for direct memory access operations involving address translation is disclosed. Example methods disclosed herein to perform direct memory access (DMA) operations include initializing a ring of descriptors, the descriptors to index respective buffers for storing, in a first memory, data to be transmitted. Such example methods also include causing prefetching of a first address translation associated with a second descriptor in the ring of descriptors to be performed after a first DMA operation is performed to retrieve, for transmission, first data from a first buffer indexed by a first descriptor in the ring of descriptors and before second data is determined to be ready for transmission, the first address translation being associated with a second DMA operation for retrieving the second data from the first memory.

Abstract translation: 公开了涉及地址转换的直接存储器访问操作的延迟减少。 用于执行直接存储器访问（DMA）操作的示例性方法包括初始化描述符环，描述符以索引各个缓冲器，用于在第一存储器中存储要发送的数据。 这样的示例方法还包括在执行第一DMA操作之后执行在执行第一DMA操作之后执行在描述符环中与第二描述符相关联的第一地址转换的预取，以从第一描述符索引的第一缓冲区中检索第一数据， 描述符的环和第二数据之前被确定为准备传输，第一地址转换与用于从第一存储器检索第二数据的第二DMA操作相关联。

公开(公告)号：US10452417B2

公开(公告)日：2019-10-22

申请号：US14721461

申请日：2015-05-26

Applicant: VMware, Inc.

Inventor： Benjamin Charles Serebrin ,  Daniel Michael Hecht

IPC: G06F9/455 ,  G06F11/34

Abstract: Methods, apparatus, and articles of manufacture to virtualize performance counters are disclosed. An example method includes dividing performance events to be counted into a plurality of classes; assigning a first virtual performance counter of a virtual machine to a first performance event type in a first one of the classes; assigning a second virtual performance counter of the virtual machine to a second performance event type in a second one of the classes different from the first class; incrementing the first virtual performance counter in response to a first occurrence of the first performance event type during direct execution of guest instructions by the virtual machine; and not incrementing the first virtual performance counter in response to a second occurrence of the first performance event type during execution of emulated instructions by a hypervisor on behalf of the virtual machine.