RFID tag dynamically adjusting clock frequency
    2.
    发明授权
    RFID tag dynamically adjusting clock frequency 有权
    RFID标签动态调整时钟频率

    公开(公告)号:US08193912B1

    公开(公告)日:2012-06-05

    申请号:US12403344

    申请日:2009-03-12

    IPC分类号: H04Q5/22

    摘要: RFID tags are configured to adjust their clock frequency in order to meet predefined limits for reply frequencies to conserve tag power. A deviation of computed tag reply frequency from a reader commanded reply frequency is used to determine an adjustment to the tag clock frequency. The tag clock frequency may be adjusted during backscatter and restored once backscattering is completed.

    摘要翻译: RFID标签被配置为调整其时钟频率,以便满足回复频率的预定限制以节省标签功率。 使用读取器命令回复频率的计算标签应答频率的偏差来确定对标签时钟频率的调整。 可以在反向散射期间调整标签时钟频率,并且一旦反向散射完成就恢复。

    RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action
    4.
    发明授权
    RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action 有权
    RFID标签电路和用于感测自身电力的方法,以预先确定所请求动作的可行性

    公开(公告)号:US07733227B1

    公开(公告)日:2010-06-08

    申请号:US11624197

    申请日:2007-01-17

    IPC分类号: G08B13/14

    摘要: Feasibility of a requested action by a reader is predetermined in an RFID tag based on an available tag power level. A pretest that is designed to consume artificially high levels of power is performed and the power level monitored to determine if a preset condition is met. The pretest may include activation of selected components such as a memory and associated support circuitry. If the preset condition is not met, the requested action is aborted and an error message transmitted to the reader.

    摘要翻译: 基于可用的标签功率电平,RFID标签中预先确定读取器所请求的动作的可行性。 执行被设计为消耗人为高电平的预测试,并且监视功率电平以确定是否满足预设条件。 预测试可以包括激活所选择的组件,例如存储器和相关联的支持电路。 如果不满足预设条件,请求的操作将中止,并将错误消息传送给读卡器。

    Devices, systems and methods for generating reference current from voltage differential having low temperature coefficient
    5.
    发明授权
    Devices, systems and methods for generating reference current from voltage differential having low temperature coefficient 有权
    用于从具有低温度系数的电压差产生参考电流的装置,系统和方法

    公开(公告)号:US07768248B1

    公开(公告)日:2010-08-03

    申请号:US11981397

    申请日:2007-10-30

    申请人: John D. Hyde

    发明人: John D. Hyde

    IPC分类号: G05F3/16

    CPC分类号: G05F3/24

    摘要: Embodiments of the invention describe a reference current generator circuit having a core circuit that includes a first transistor in a first current path for conduct a first current and a second transistor in a second current path for conduct a second current. The second transistor has a threshold voltage that is different from the threshold voltage of the first transistor by at least 10%. The voltage differential between the first and second transistors generate a voltage across a resistive component coupled in series with the second transistor in the second current path.

    摘要翻译: 本发明的实施例描述了具有核心电路的参考电流发生器电路,该核心电路包括用于在第二电流路径中传导第一电流的第一电流路径中的第一晶体管和用于导通第二电流的第二晶体管。 第二晶体管具有与第一晶体管的阈值电压不同的阈值电压至少10%。 第一和第二晶体管之间的电压差在与第二电流路径中的第二晶体管串联耦合的电阻分量上产生电压。

    INTERFERENCE REJECTION IN RFID TAGS
    6.
    发明申请
    INTERFERENCE REJECTION IN RFID TAGS 有权
    RFID标签中的干扰抑制

    公开(公告)号:US20100182129A1

    公开(公告)日:2010-07-22

    申请号:US12749648

    申请日:2010-03-30

    IPC分类号: H04Q5/22

    摘要: RFID tags, tag circuits, and methods are provided that reject at least in part the distortion caused to wireless signals by interference in the environment. When the received RF wave is converted into an unfiltered input (971), a filtered output (972) is generated that does not include an artifact feature deriving from the distortion. The filtered output is used instead of the unfiltered input, which results in tag operation as if there were less interference in the environment, or none at all.

    摘要翻译: 提供RFID标签,标签电路和方法,其至少部分地通过在环境中的干扰而拒绝对无线信号造成的失真。 当接收的RF波被转换成未滤波的输入(971)时,生成不包括从失真导出的伪影特征的滤波输出(972)。 使用滤波输出而不是未过滤的输入,这导致标签操作,就好像环境中的干扰较少,或者根本没有。

    Wafer level testing for RFID tags
    7.
    发明授权
    Wafer level testing for RFID tags 有权
    RFID标签的晶圆级测试

    公开(公告)号:US07312622B2

    公开(公告)日:2007-12-25

    申请号:US11014523

    申请日:2004-12-15

    IPC分类号: G01R31/26

    摘要: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.

    摘要翻译: 披露了适用于无处不在的计算时代的在晶片测试的技术。 所公开的发明特征之一是:1)用于并行测试测序的晶圆测试探针着陆区域的聚类; 2)在沿着晶片划线区域延伸的晶片测试布线上; 3)晶片测试布线,可以刻划,但阻止污染物扩散到产品模具中; 4)RFID标签设计,允许进行片上测试而不施加实质的半导体表面积损失; 5)RFID标签设计,包括用于RFID标签的非易失性存储器的内置自检(BIST)电路。

    pFET nonvolatile memory
    8.
    发明授权
    pFET nonvolatile memory 有权
    pFET非易失性存储器

    公开(公告)号:US07221596B2

    公开(公告)日:2007-05-22

    申请号:US10839985

    申请日:2004-05-05

    IPC分类号: G11C16/06

    摘要: A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/information storage. A control capacitor structure (CCS) having terminals coupled to a first voltage source and the FG and a tunneling capacitor structure (TCS) having terminals coupled to a second voltage source and the FG are utilized in each embodiment. The CCS has much more capacitance than the TCS. Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the CCS and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the FG, thus controlling the charge on the FG and the information stored thereon.

    摘要翻译: 使用其源极连接到电源(Vdd)的浮栅(FG)pFET读出晶体管(RT)构成非易失性存储单元,其漏极提供可被感测以确定单元状态的电流。 RT的门提供充电/信息存储。 具有耦合到第一电压源的端子和具有耦合到第二电压源和FG的端子的隧道电容器结构(TCS)的控制电容器结构(CCS)在每个实施例中被使用。 CCS具有比TCS多得多的电容。 对施加到第一电压源和第二电压源(和Vdd)的电压的操纵控制跨越CCS和pFET电介质的电场,并且因此Fowler-Nordheim隧道电子进入FG和FG,从而控制FG上的电荷 以及存储在其上的信息。

    Method and apparatus for controlled persistent ID flag for RFID applications
    9.
    发明授权
    Method and apparatus for controlled persistent ID flag for RFID applications 有权
    用于RFID应用的受控持续ID标志的方法和装置

    公开(公告)号:US07116240B2

    公开(公告)日:2006-10-03

    申请号:US10921758

    申请日:2004-08-18

    申请人: John D. Hyde

    发明人: John D. Hyde

    IPC分类号: G08B21/00

    CPC分类号: G06K19/0723

    摘要: A Radio-Frequency Identification (RFID) transponder is provided. The RFID transponder may include a basic ID flag circuit having a VDD voltage node, an output voltage node, and a capacitor coupled to the VDD voltage node and the output voltage node to store an ID flag. The persistence duration of the state of the ID flag is controlled by maintaining a charge and leakage circuit. The charge and leakage circuit includes an NMOS device having a source, a drain and a gate, the source node of the NMOS device being coupled to the capacitor and the drain node of the NMOS device being coupled to a first CMOS inverter. The first CMOS inverter is powered by a regulated supply voltage such that the voltage on the capacitor is not dependent on the forward voltage drop of the NMOS device.

    摘要翻译: 提供射频识别(RFID)应答器。 RFID应答器可以包括具有VDD电压节点的基本ID标志电路,输出电压节点和耦合到VDD电压节点的电容器和输出电压节点以存储ID标志。 通过维持充电和泄漏电路来控制ID标志的状态的持续持续时间。 充电和泄漏电路包括具有源极,漏极和栅极的NMOS器件,NMOS器件的源极耦合到电容器,NMOS器件的漏极节点耦合到第一CMOS反相器。 第一个CMOS反相器由稳压电源供电,使得电容上的电压不依赖于NMOS器件的正向压降。

    RFID tags with synchronous power rectifier
    10.
    发明授权
    RFID tags with synchronous power rectifier 有权
    具有同步电源整流器的RFID标签

    公开(公告)号:US08344857B1

    公开(公告)日:2013-01-01

    申请号:US13307098

    申请日:2011-11-30

    IPC分类号: H04Q5/22

    摘要: The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The rectifier is constructed from a pair of complementary MOS transistors. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating region. During the same time additional control signals are applied to the gates of the transistors, the control signals are synchronous, but out of phase, with each other.

    摘要翻译: 本公开提供了一种用于射频识别标签电路的功率整流器。 整流器由一对互补MOS晶体管构成。 晶体管的栅极具有施加到它们的预定电压。 施加的电压将晶体管偏置到其活动工作区域附近。 在同一时间,附加的控制信号被施加到晶体管的栅极,控制信号是同步的,但彼此相位不同。