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    pFET nonvolatile memory
    1.
    发明授权
    pFET nonvolatile memory 有权
    pFET非易失性存储器

    公开(公告)号：US07221596B2

    公开(公告)日：2007-05-22

    申请号：US10839985

    申请日：2004-05-05

    申请人： Alberto Pesavento ,  Frédéric J. Bernard ,  John D. Hyde

    发明人： Alberto Pesavento ,  Frédéric J. Bernard ,  John D. Hyde

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0441 ,  G11C16/28 ,  G11C2216/10 ,  H01L27/115 ,  H01L29/7883

    摘要： A nonvolatile memory cell is constructed using a floating-gate (FG) pFET Readout Transistor (RT) having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine a cell state. The gate of the RT provides for charge/information storage. A control capacitor structure (CCS) having terminals coupled to a first voltage source and the FG and a tunneling capacitor structure (TCS) having terminals coupled to a second voltage source and the FG are utilized in each embodiment. The CCS has much more capacitance than the TCS. Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the CCS and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the FG, thus controlling the charge on the FG and the information stored thereon.

    摘要翻译： 使用其源极连接到电源（Vdd）的浮栅（FG）pFET读出晶体管（RT）构成非易失性存储单元，其漏极提供可被感测以确定单元状态的电流。 RT的门提供充电/信息存储。 具有耦合到第一电压源的端子和具有耦合到第二电压源和FG的端子的隧道电容器结构（TCS）的控制电容器结构（CCS）在每个实施例中被使用。 CCS具有比TCS多得多的电容。 对施加到第一电压源和第二电压源（和Vdd）的电压的操纵控制跨越CCS和pFET电介质的电场，并且因此Fowler-Nordheim隧道电子进入FG和FG，从而控制FG上的电荷 以及存储在其上的信息。

    PFET Nonvolatile Memory
    3.
    发明申请
    PFET Nonvolatile Memory 有权
    PFET非易失性存储器

    公开(公告)号：US20120099380A1

    公开(公告)日：2012-04-26

    申请号：US13342834

    申请日：2012-01-03

    申请人： Alberto Pesavento ,  John D. Hyde

    发明人： Alberto Pesavento ,  John D. Hyde

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/0433 ,  G11C11/005 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2216/10 ,  G11C2216/26

    摘要： A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

    摘要翻译： 使用其源极连接到电源（Vdd）的浮栅pFET读出晶体管构造非易失性存储单元，其漏极提供电流，其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储，可用于表示诸如二进制位之类的信息。 耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。 施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场，从而Fowler-Nordheim在浮栅上和从浮栅上隧穿隧道，控制浮栅上的电荷和信息 存储在其上。

    PFET nonvolatile memory
    5.
    发明授权
    PFET nonvolatile memory 有权
    PFET非易失性存储器

    公开(公告)号：US08416630B2

    公开(公告)日：2013-04-09

    申请号：US13342834

    申请日：2012-01-03

    申请人： Alberto Pesavento ,  John D. Hyde

    发明人： Alberto Pesavento ,  John D. Hyde

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0433 ,  G11C11/005 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2216/10 ,  G11C2216/26

    摘要： A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

    摘要翻译： 使用其源极连接到电源（Vdd）的浮栅pFET读出晶体管构造非易失性存储单元，其漏极提供电流，其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储，可用于表示诸如二进制位之类的信息。 耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。 施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场，从而Fowler-Nordheim隧穿电子在浮栅上和离开浮栅，控制浮栅上的电荷和信息 存储在其上。

    RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action
    6.
    发明授权
    RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action 有权
    RFID标签电路和用于感测自身电力的方法，以预先确定所请求动作的可行性

    公开(公告)号：US07733227B1

    公开(公告)日：2010-06-08

    申请号：US11624197

    申请日：2007-01-17

    申请人： Alberto Pesavento ,  Vadim Gutnik ,  John D. Hyde

    发明人： Alberto Pesavento ,  Vadim Gutnik ,  John D. Hyde

    IPC分类号： G08B13/14

    CPC分类号： G06K7/0008 ,  G06K19/0707 ,  G06K19/0712 ,  G06K19/07749

    摘要： Feasibility of a requested action by a reader is predetermined in an RFID tag based on an available tag power level. A pretest that is designed to consume artificially high levels of power is performed and the power level monitored to determine if a preset condition is met. The pretest may include activation of selected components such as a memory and associated support circuitry. If the preset condition is not met, the requested action is aborted and an error message transmitted to the reader.

    摘要翻译： 基于可用的标签功率电平，RFID标签中预先确定读取器所请求的动作的可行性。 执行被设计为消耗人为高电平的预测试，并且监视功率电平以确定是否满足预设条件。 预测试可以包括激活所选择的组件，例如存储器和相关联的支持电路。 如果不满足预设条件，请求的操作将中止，并将错误消息传送给读卡器。

    pFET nonvolatile memory
    7.
    发明授权
    pFET nonvolatile memory 有权
    pFET非易失性存储器

    公开(公告)号：US08111558B2

    公开(公告)日：2012-02-07

    申请号：US11865777

    申请日：2007-10-02

    申请人： Alberto Pesavento ,  John D. Hyde

    发明人： Alberto Pesavento ,  John D. Hyde

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0433 ,  G11C11/005 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2216/10 ,  G11C2216/26

    摘要： A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

    摘要翻译： 使用其源极连接到电源（Vdd）的浮栅pFET读出晶体管构造非易失性存储单元，其漏极提供电流，其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储，可用于表示诸如二进制位之类的信息。 耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。 施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场，从而Fowler-Nordheim在浮栅上和从浮栅上隧穿隧道，控制浮栅上的电荷和信息 存储在其上。

    PFET NONVOLATILE MEMORY
    8.
    发明申请
    PFET NONVOLATILE MEMORY 有权
    PFET非易失性存储器

    公开(公告)号：US20080175050A1

    公开(公告)日：2008-07-24

    申请号：US11865777

    申请日：2007-10-02

    申请人： ALBERTO PESAVENTO ,  John D. Hyde

    发明人： ALBERTO PESAVENTO ,  John D. Hyde

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/0433 ,  G11C11/005 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3468 ,  G11C16/3477 ,  G11C16/3486 ,  G11C2216/10 ,  G11C2216/26

    摘要： A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current, which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage, which can be used to represent information such as binary bits. A control capacitor coupled between a first voltage source and the floating gate and a tunneling capacitor between a second voltage source and the floating gate are fabricated so that the control capacitor has much more capacitance than the tunneling capacitor. Manipulation of the voltages applied to the first voltage source and second voltage source controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons on and off the floating gate, controlling the charge on the floating gate and the information stored thereon.

    摘要翻译： 使用其源极连接到电源（Vdd）的浮栅pFET读出晶体管构造非易失性存储单元，其漏极提供电流，其可以被感测以确定单元的状态。 pFET读出晶体管的栅极提供电荷存储，可用于表示诸如二进制位之类的信息。 耦合在第一电压源和浮动栅极之间的控制电容器和在第二电压源和浮置栅极之间的隧道电容器被制造成使得控制电容器具有比隧道电容器多得多的电容。 施加到第一电压源和第二电压源的电压的操作控制电容器结构和pFET电介质两端的电场，从而Fowler-Nordheim隧穿电子在浮栅上和离开浮栅，控制浮栅上的电荷和信息 存储在其上。

    RFID tag dynamically adjusting clock frequency
    9.
    发明授权
    RFID tag dynamically adjusting clock frequency 有权
    RFID标签动态调整时钟频率

    公开(公告)号：US08193912B1

    公开(公告)日：2012-06-05

    申请号：US12403344

    申请日：2009-03-12

    申请人： Vadim Gutnik ,  Scott A. Cooper ,  John D. Hyde

    发明人： Vadim Gutnik ,  Scott A. Cooper ,  John D. Hyde

    IPC分类号： H04Q5/22

    CPC分类号： G06K19/0701 ,  H04Q2213/13095

    摘要： RFID tags are configured to adjust their clock frequency in order to meet predefined limits for reply frequencies to conserve tag power. A deviation of computed tag reply frequency from a reader commanded reply frequency is used to determine an adjustment to the tag clock frequency. The tag clock frequency may be adjusted during backscatter and restored once backscattering is completed.

    摘要翻译： RFID标签被配置为调整其时钟频率，以便满足回复频率的预定限制以节省标签功率。 使用读取器命令回复频率的计算标签应答频率的偏差来确定对标签时钟频率的调整。 可以在反向散射期间调整标签时钟频率，并且一旦反向散射完成就恢复。

    Devices, systems and methods for generating reference current from voltage differential having low temperature coefficient
    10.
    发明授权
    Devices, systems and methods for generating reference current from voltage differential having low temperature coefficient 有权
    用于从具有低温度系数的电压差产生参考电流的装置，系统和方法

    公开(公告)号：US07768248B1

    公开(公告)日：2010-08-03

    申请号：US11981397

    申请日：2007-10-30

    申请人： John D. Hyde

    发明人： John D. Hyde

    IPC分类号： G05F3/16

    CPC分类号： G05F3/24

    摘要： Embodiments of the invention describe a reference current generator circuit having a core circuit that includes a first transistor in a first current path for conduct a first current and a second transistor in a second current path for conduct a second current. The second transistor has a threshold voltage that is different from the threshold voltage of the first transistor by at least 10%. The voltage differential between the first and second transistors generate a voltage across a resistive component coupled in series with the second transistor in the second current path.

    摘要翻译： 本发明的实施例描述了具有核心电路的参考电流发生器电路，该核心电路包括用于在第二电流路径中传导第一电流的第一电流路径中的第一晶体管和用于导通第二电流的第二晶体管。 第二晶体管具有与第一晶体管的阈值电压不同的阈值电压至少10％。 第一和第二晶体管之间的电压差在与第二电流路径中的第二晶体管串联耦合的电阻分量上产生电压。