公开(公告)号：US08068566B2

公开(公告)日：2011-11-29

申请号：US11888228

申请日：2007-07-31

Applicant: Raghavan Sudhakar ,  Veerendra Bhora ,  Kamal J. Koshy

Inventor： Raghavan Sudhakar ,  Veerendra Bhora ,  Kamal J. Koshy

IPC: H03D1/00

CPC classification number: H04L5/0023 ,  H04L1/0054 ,  H04L1/0631 ,  H04L1/0643

Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple detection modes and multiple MIMO configurations.

Abstract translation: 通常，在一个方面，本公开描述了将与多输入多输出（MIMO）接收机一起使用的统一简化最大似然检测器来估计发射信号。 统一检测器包括能够被用于多个检测模式和多个MIMO配置的公共框架。

公开(公告)号：US20090034662A1

公开(公告)日：2009-02-05

申请号：US11888228

申请日：2007-07-31

Applicant: Raghavan Sudhakar ,  Veerendra Bhora ,  Kamal J. Koshy

Inventor： Raghavan Sudhakar ,  Veerendra Bhora ,  Kamal J. Koshy

IPC: H03D1/02

CPC classification number: H04L5/0023 ,  H04L1/0054 ,  H04L1/0631 ,  H04L1/0643

Abstract: In general, in one aspect, the disclosure describes a unified simplified maximum likelihood detector to be utilized with multiple input multiple output (MIMO) receivers to estimate transmitted signals. The unified detector includes a common framework capable of being utilized for multiple spatial operational modes and multiple MIMO configurations.

Abstract translation: 通常，在一个方面，本公开描述了将与多输入多输出（MIMO）接收机一起使用的统一简化最大似然检测器来估计发射信号。 统一检测器包括能够用于多个空间操作模式和多个MIMO配置的公共框架。

公开(公告)号：US07895506B2

公开(公告)日：2011-02-22

申请号：US11612350

申请日：2006-12-18

Applicant: Veerendra Bhora ,  Raghavan Sudhakar

Inventor： Veerendra Bhora ,  Raghavan Sudhakar

IPC: H03M13/03

CPC classification number: H04L1/0051 ,  H04L1/06

Abstract: Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.

Abstract translation: 具有早退条件检测的迭代解码器和解码方法的实施例在此通常被描述。 可以描述和要求保护其他实施例。 在一些实施例中，在迭代解码器的一个或多个半迭代之后从经解码的比特生成第一码字，在迭代解码器的附加半迭代之后的解码比特中的第二码字，并将第一和第二码字与 确定解码的比特是否有效。 在一些实施例中，基于估计的信噪比（SNR）和调制电平来选择双码或三码字匹配。

公开(公告)号：US20080148125A1

公开(公告)日：2008-06-19

申请号：US11612350

申请日：2006-12-18

Applicant: Veerendra Bhora ,  Raghavan Sudhakar

Inventor： Veerendra Bhora ,  Raghavan Sudhakar

IPC: G06F11/10

CPC classification number: H04L1/0051 ,  H04L1/06

Abstract: Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.

Abstract translation: 具有早退条件检测的迭代解码器和解码方法的实施例在此通常被描述。 可以描述和要求保护其他实施例。 在一些实施例中，在迭代解码器的一个或多个半迭代之后从经解码的比特生成第一码字，在迭代解码器的附加半迭代之后的解码比特中的第二码字，并将第一和第二码字与 确定解码的比特是否有效。 在一些实施例中，基于估计的信噪比（SNR）和调制电平来选择双码或三码字匹配。

公开(公告)号：US08301679B2

公开(公告)日：2012-10-30

申请号：US11723082

申请日：2007-03-16

Applicant: Raghavan Sudhakar

Inventor： Raghavan Sudhakar

IPC: G06F7/38

CPC classification number: G06F7/556 ,  G06F1/02 ,  G06F2101/10

Abstract: Efficiency of computation of logarithmic and exponential functions may be improved using multiplication by pre-computed coefficients to obtain intermediate products.

Abstract translation: 对数和指数函数的计算效率可以通过使用预先计算的系数乘以获得中间产物来提高。

公开(公告)号：US07853858B2

公开(公告)日：2010-12-14

申请号：US11617251

申请日：2006-12-28

Applicant: Kamal J Koshy ,  Raghavan Sudhakar ,  Prasad Modali

Inventor： Kamal J Koshy ,  Raghavan Sudhakar ,  Prasad Modali

IPC: H03M13/03

CPC classification number: H03M13/235 ,  H03M13/2957 ,  H03M13/2987 ,  H03M13/2993 ,  H03M13/6544

Abstract: Embodiments of encoding input data into parity data in mechanisms are described generally herein. Other embodiments may be described and claimed.

Abstract translation: 本文一般地描述将输入数据编码到机构中的奇偶校验数据的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US06760830B2

公开(公告)日：2004-07-06

申请号：US09751507

申请日：2000-12-29

Applicant: Ryo Inoue ,  Ravi Kolagotla ,  Raghavan Sudhakar

Inventor： Ryo Inoue ,  Ravi Kolagotla ,  Raghavan Sudhakar

IPC: G06F1200

CPC classification number: G06F5/10 ,  G06F7/72 ,  G06F9/3552 ,  G06F2205/106

Abstract: In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I+M =B+L and an uncorrected module address when B

Abstract translation: 在一个实施例中，描述了一种用于处理器的模寻址单元，其包括多个加法器，以并行生成未校正的目标模地址和至少一个校正的目标模数地址。 比较器选择目标模数地址中的一个作为循环缓冲器的基址（b），循环缓冲器的长度（L），索引地址（I）和修改值（M）的函数。 在一个实施例中，当I + M = B + L时第二校正目标模地址和当B <= I + M