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55 条记录 (耗时 0.038 秒)

    Switching circuits
    3.
    发明授权
    Switching circuits 有权
    开关电路

    公开(公告)号：US07034609B2

    公开(公告)日：2006-04-25

    申请号：US10712746

    申请日：2003-11-12

    申请人： Lars Risbo ,  Anker Josefsen

    发明人： Lars Risbo ,  Anker Josefsen

    IPC分类号： H03F3/38

    CPC分类号： H03F3/217 ,  H03F3/45085 ,  H03F2203/45636

    摘要： A technique to implement removal of dead time control circuitry from the back-end of a digital switching amplifier system 100 and add dead time control circuitry on the front-end digital modulator chip. The front-end dead time control circuitry adaptively adjusts timing of the output PWM control signals 124 to optimize performance and power consumption, i.e. operate with minimum dead time for all transitions. The front-end dead time control circuitry controls all propagation delays associated with the digital switching amplifier system 100.

    摘要翻译： 一种实现从数字开关放大器系统100的后端去除死区时间控制电路并在前端数字调制器芯片上增加死区时间控制电路的技术。 前端死区时间控制电路自适应地调节输出PWM控制信号124的定时，以优化性能和功耗，即以最小死区时间进行所有转换。 前端死区时间控制电路控制与数字开关放大器系统100相关联的所有传播延迟。

    Digital audio receiver with reduced AM interference
    4.
    发明授权
    Digital audio receiver with reduced AM interference 有权
    具有降低AM干扰的数字音频接收器

    公开(公告)号：US07809346B2

    公开(公告)日：2010-10-05

    申请号：US11118831

    申请日：2005-04-29

    申请人： Lars Risbo ,  Luis E. Ossa

    发明人： Lars Risbo ,  Luis E. Ossa

    IPC分类号： H04B1/10

    CPC分类号： H03F3/217

    摘要： A digital audio system including a digital audio amplifier with reduced AM interference. The digital audio amplifier includes a pulse-width-modulation (PWM) processor in which a digital datastream is upsampled by an interpolation filter. A sample rate converter resamples the upsampled datastream to produce a datastream at a converted sampling frequency, or PWM frame rate. The converted datastream is then applied to pulse-width-modulation circuitry which generates a PWM signal at the PWM frame rate. The sample rate converter resamples according to a sample rate conversion ratio associated with the AM tuned frequency. For example, the sample rate conversion ratio can be selected so that the PWM frame rate and its lower harmonics avoid an AM tuned frequency, any intermediate frequency in the AM tuner, and also an image frequency in the tuner.

    摘要翻译： 一种数字音频系统，包括具有降低的AM干扰的数字音频放大器。 数字音频放大器包括脉冲宽度调制（PWM）处理器，其中数字数据流被内插滤波器上采样。 采样率转换器对上采样的数据流重新采样，以转换采样频率或PWM帧速率产生数据流。 转换的数据流然后被应用于以PWM帧速率产生PWM信号的脉宽调制电路。 采样率转换器根据与AM调谐频率相关的采样率转换比重新采样。 例如，可以选择采样率转换比，使得PWM帧速率及其低次谐波避免AM调谐频率，AM调谐器中的任何中频，以及调谐器中的图像频率。

    Switching circuits
    5.
    发明申请
    Switching circuits 有权
    开关电路

    公开(公告)号：US20050099226A1

    公开(公告)日：2005-05-12

    申请号：US10712746

    申请日：2003-11-12

    申请人： Lars Risbo ,  Anker Josefsen

    发明人： Lars Risbo ,  Anker Josefsen

    IPC分类号： H03F3/217 ,  H03F3/38 ,  H03F3/45

    CPC分类号： H03F3/217 ,  H03F3/45085 ,  H03F2203/45636

    摘要： A technique to implement removal of dead time control circuitry from the back-end of a digital switching amplifier system 100 and add dead time control circuitry on the front-end digital modulator chip. The front-end dead time control circuitry adaptively adjusts timing of the output PWM control signals 124 to optimize performance and power consumption, i.e. operate with minimum dead time for all transitions. The front-end dead time control circuitry controls all propagation delays associated with the digital switching amplifier system 100.

    摘要翻译： 一种实现从数字开关放大器系统100的后端去除死区时间控制电路并在前端数字调制器芯片上增加死区时间控制电路的技术。 前端死区时间控制电路自适应地调节输出PWM控制信号124的定时，以优化性能和功耗，即以最小死区时间进行所有转换。 前端死区时间控制电路控制与数字开关放大器系统100相关联的所有传播延迟。

    Thermal Control of Voice Coils in Loudspeakers
    6.
    发明申请
    Thermal Control of Voice Coils in Loudspeakers 有权
    扬声器中音圈的热控制

    公开(公告)号：US20130077794A1

    公开(公告)日：2013-03-28

    申请号：US13247538

    申请日：2011-09-28

    申请人： Lars Risbo ,  Milind Anil Borkar ,  Theis Buchwald Christiansen

    发明人： Lars Risbo ,  Milind Anil Borkar ,  Theis Buchwald Christiansen

    IPC分类号： H03G11/00

    CPC分类号： H03G11/008 ,  H04R3/007 ,  H04R2499/15

    摘要： In an embodiment of the invention, the voice coil of an electro dynamic transducer is protected against thermal overload by estimating the temperature of a magnet in the electro dynamic transducer. When a power limit based on the temperature of the magnet and on a predetermined voice coil temperature limit is reached by an audio signal, the power applied to the voice coil is reduced.

    摘要翻译： 在本发明的实施例中，通过估计电动变换器中的磁体的温度来保护电动换能器的音圈免受热过载。 当通过音频信号达到基于磁体的温度和预定音圈温度极限的功率限制时，施加到音圈的功率减小。

    High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth
    7.
    发明授权
    High performance analog charge pumped phase locked loop (PLL) architecture with process and temperature compensation in closed loop bandwidth 有权
    高性能模拟电荷泵浦锁相环（PLL）架构，在闭环带宽中具有过程和温度补偿

    公开(公告)号：US07167056B2

    公开(公告)日：2007-01-23

    申请号：US10955064

    申请日：2004-09-30

    申请人： Lieyi Fang ,  Asit Shankar ,  Lars Risbo

    发明人： Lieyi Fang ,  Asit Shankar ,  Lars Risbo

    IPC分类号： H03K3/03 ,  H03B5/12 ,  H03L7/093

    CPC分类号： H03L7/0995 ,  H03L7/0891 ,  H03L2207/04

    摘要： The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).

    摘要翻译： 本发明实现了在闭环带宽中具有过程和温度补偿的高性能模拟电荷泵浦锁相环（PLL）（10）的技术优点。 PLL通过不依赖于过程和温度变化产生产品K VCO，从而减小带宽和稳定性的变化。 PLL实现了比现有PLL架构更高的性能，实现高达至少110 dB的高动态范围，从而可以利用该PLL实现PWM D类放大器。 使用模拟电荷泵（16）时，PLL具有恒定的带宽和阻尼因子。

    Multiple coefficient filter banks for digital audio processing
    8.
    发明申请
    Multiple coefficient filter banks for digital audio processing 审中-公开
    用于数字音频处理的多个系数滤波器组

    公开(公告)号：US20060251197A1

    公开(公告)日：2006-11-09

    申请号：US11120724

    申请日：2005-05-03

    申请人： David Zaucha ,  Douglas Roberson ,  Josey Angilivelil ,  Lars Risbo

    发明人： David Zaucha ,  Douglas Roberson ,  Josey Angilivelil ,  Lars Risbo

    IPC分类号： H04B1/10

    CPC分类号： H04S3/008

    摘要： A digital audio processor (20) is disclosed, in which digital filter coefficients associated with a plurality of sampling frequencies are stored in a plurality of coefficient memory banks (55). A controller in the digital audio processor (20) selects one of the coefficient memory banks (55) for use in the digital signal processing channels (44). In a manual mode, this selection is in response to a manual selection entry in a bank control register (41). In an automatic mode, indicated by a specific entry in the bank control register (41), sample rate detector circuitry (54) detects the sampling frequency relative to an external reference, such as a crystal (XTL); the appropriate one of the coefficient memory banks (55) is then selected based on sampling frequency associations stored in rate select register (43) in the controller (40).

    摘要翻译： 公开了一种数字音频处理器（20），其中与多个采样频率相关联的数字滤波器系数被存储在多个系数存储器组（55）中。 数字音频处理器（20）中的控制器选择用于数字信号处理通道（44）中的一个系数存储器组（55）。 在手动模式中，该选择是响应于银行控制寄存器（41）中的手动选择条目。 在由存储体控制寄存器（41）中的特定条目指示的自动模式下，采样率检测器电路（54）检测相对于诸如晶体（XTL）的外部参考的采样频率; 然后基于存储在控制器（40）中的速率选择寄存器（43）中的采样频率关联来选择系数存储体（55）中适当的一个。

    Detection of DC output levels from a class D amplifier
    9.
    发明授权
    Detection of DC output levels from a class D amplifier 有权
    从D类放大器检测直流输出电平

    公开(公告)号：US07078964B2

    公开(公告)日：2006-07-18

    申请号：US10963239

    申请日：2004-10-12

    申请人： Lars Risbo ,  James Teng

    发明人： Lars Risbo ,  James Teng

    IPC分类号： H03F3/38

    CPC分类号： H03F3/217 ,  H03F1/52

    摘要： A class AD audio amplifier system (10) with DC output detection logic (26) is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which includes a pulse-width-modulator (PWM) (24). The DC detection logic (26) includes a sigma-delta modulator (60) and a digital low-pass filter (62) that monitors the PWM output signals from the PWM modulators (24). The sigma-delta modulator (60) operates at a first clock frequency, while the low-pass filter (62) operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level (THRSH) to determine whether the amplitude of a DC component at the PWM output is sufficiently high to constitute a fault. If so, a fault detection signal (DC_DET) is issued, and the PWM modulators (24) are disabled to prevent unsafe conditions in the system (10).

    摘要翻译： 公开了具有DC输出检测逻辑（26）的AD类音频放大器系统（10）。 放大器系统（10）包括多个音频通道（20），每个音频通道包括脉宽调制器（PWM）（24）。 直流检测逻辑（26）包括一个Σ-Δ调制器（60）和数字低通滤波器（62），用于监视来自PWM调制器（24）的PWM输出信号。 Σ-Δ调制器（60）以第一时钟频率工作，而低通滤波器（62）以低得多的时钟频率工作，从而抑制AC音频分量，PWM谐波和Σ-Δ量化误差 直流检测。 将调制的滤波信号与阈值电平（THRSH）进行比较，以确定PWM输出处的DC分量的幅度是否足够高以构成故障。 如果是，则发出故障检测信号（DC_DET），并且PWM调制器（24）被禁用以防止系统（10）中的不安全状况。

    Shaping inter-symbol-interference in sigma delta converter
    10.
    发明授权
    Shaping inter-symbol-interference in sigma delta converter 有权
    在Σ-Δ转换器中形成符号间干扰

    公开(公告)号：US08144043B2

    公开(公告)日：2012-03-27

    申请号：US12769629

    申请日：2010-04-28

    申请人： Lars Risbo ,  Rahmi Hezar ,  Burak Kelleci ,  Anker Bjoern-Josefsen

    发明人： Lars Risbo ,  Rahmi Hezar ,  Burak Kelleci ,  Anker Bjoern-Josefsen

    IPC分类号： H03M1/66

    CPC分类号： H03M7/3006 ,  H03M1/0668 ,  H03M1/74 ,  H03M3/502

    摘要： A signal converting system is described that has a multi-segment digital to analog converter coupled to one or more error shaping loops. Each error shaping loop includes a quantizer with a feedback loop configured to generate a control signal responsive to a stream of symbols and to an error signal. Each error shaping loop also includes an inter-symbol-interference (ISI) shaping loop coupled to receive the control signal and to produce an ISI portion of the error signal that is responsive to inter-symbol transition rate.

    摘要翻译： 描述了具有耦合到一个或多个错误整形环路的多段数模转换器的信号转换系统。 每个错误整形循环包括具有反馈回路的量化器，其被配置为响应于符号流和误差信号产生控制信号。 每个错误整形环路还包括码元间干扰（ISI）整形环路，其被耦合以接收控制信号并产生响应于符号间转换速率的误差信号的ISI部分。