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    Power cell, power cell circuit for a power amplifier and a method of making and using a power cell
    1.
    发明授权
    Power cell, power cell circuit for a power amplifier and a method of making and using a power cell 有权
    功率单元，功率放大器的功率单元电路以及制造和使用功率单元的方法

    公开(公告)号：US09490248B2

    公开(公告)日：2016-11-08

    申请号：US13753995

    申请日：2013-01-30

    Applicant: Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Jun-De Jin

    Inventor： Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Jun-De Jin

    IPC: H01L29/66 ,  H01L29/772 ,  H01L27/06 ,  H03K17/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L27/0629 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/66484 ,  H01L29/66636 ,  H01L29/7832 ,  H03K17/102 ,  H03K2217/0018

    Abstract: A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer.

    Abstract translation: 一种功率单元，包括形成在基板中的具有第一掺杂剂类型的隔离区域。 功率单元还包括具有不同于在隔离区上形成的第一掺杂剂类型的第二掺杂剂型的底栅和在底栅上形成的具有第一掺杂剂类型的沟道层。 功率单元还包括在沟道层中形成的具有第一掺杂剂类型的源极/漏极区域和形成在沟道层和源极/漏极区域周围的具有第二掺杂剂类型的第一阱区域，以及与第一阱区域电连接的第一阱区域 底门 功率单元还包括具有第一掺杂剂类型的第二阱区，该第二阱区形成在沟道层周围并与隔离区接触并形成在沟道层上的栅极结构。

    High-k transformers extending into multiple dielectric layers
    2.
    发明授权
    High-k transformers extending into multiple dielectric layers 有权
    高k变压器延伸到多个电介质层

    公开(公告)号：US09424970B2

    公开(公告)日：2016-08-23

    申请号：US12955527

    申请日：2010-11-29

    Applicant: Jun-De Jin ,  Tzu-Jin Yeh

    Inventor： Jun-De Jin ,  Tzu-Jin Yeh

    IPC: H01F5/00 ,  H01F27/28 ,  H01F17/00

    CPC classification number: H01F5/003 ,  H01F27/2804 ,  H01F2017/0046 ,  H01F2027/2809

    Abstract: A device includes a first plurality of dielectric layers over a substrate and a second plurality of dielectric layers over the first plurality of dielectric layers. A metal inductor includes a first metal portion, a second metal portion, a third metal portion, and a fourth metal portion, wherein each of the first, the second, the third, and the fourth metal portions extends into the first and the second plurality of dielectric layers. A first metal bridge connects the first metal portion to the second metal portion, wherein the first metal bridge extends into the first plurality of dielectric layers and not into the second plurality of dielectric layers. A second metal bridge connects the third metal portion to the fourth metal portion, wherein the second metal bridge extends into the second plurality of dielectric layers and not into the first plurality of dielectric layers.

    Abstract translation: 一种器件包括在衬底上的第一多个电介质层和在第一多个电介质层上的第二多个电介质层。 金属电感器包括第一金属部分，第二金属部分，第三金属部分和第四金属部分，其中第一，第二，第三和第四金属部分中的每一个延伸到第一和第二金属部分 的介电层。 第一金属桥将第一金属部分连接到第二金属部分，其中第一金属桥延伸到第一多个电介质层中，而不延伸到第二多个电介质层中。 第二金属桥将第三金属部分连接到第四金属部分，其中第二金属桥延伸到第二多个介电层中，而不延伸到第一多个电介质层中。

    ESD block isolation by RF choke
    4.
    发明授权
    ESD block isolation by RF choke 有权
    ESD阻隔隔离ESD

    公开(公告)号：US08958185B2

    公开(公告)日：2015-02-17

    申请号：US13029240

    申请日：2011-02-17

    Applicant: Ming Hsien Tsai ,  Jun-De Jin ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh

    Inventor： Ming Hsien Tsai ,  Jun-De Jin ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh

    IPC: H02H9/00 ,  H01L27/02 ,  H02H9/04 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

    CPC classification number: H01L27/0288 ,  H02H9/046

    Abstract: A circuit includes a first node configured to receive a radio frequency (“RF”) signal, a first electrostatic discharge (ESD) protection circuit coupled to a first voltage supply rail for an RF circuit and to a second node, and a second ESD protection circuit coupled to the second node and to a second voltage supply node for the RF circuit. An RF choke circuit is coupled to the second node and to a third node disposed between the first node and the RF circuit.

    Abstract translation: 电路包括被配置为接收射频（“RF”）信号的第一节点，耦合到用于RF电路的第一电压供电轨和第二节点的第一静电放电（ESD）保护电路，以及第二ESD保护 耦合到第二节点的电路和用于RF电路的第二电压供应节点。 RF扼流电路耦合到第二节点和设置在第一节点和RF电路之间的第三节点。

    Switched Capacitor Array for Voltage Controlled Oscillator
    7.
    发明申请
    Switched Capacitor Array for Voltage Controlled Oscillator 审中-公开
    用于压控振荡器的开关电容阵列

    公开(公告)号：US20120286888A1

    公开(公告)日：2012-11-15

    申请号：US13103592

    申请日：2011-05-09

    Applicant: Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    Inventor： Hsieh-Hung Hsieh ,  Ming Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC: H03B5/12 ,  H03H11/00

    CPC classification number: H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/0266

    Abstract: A system comprises a voltage controlled oscillator comprising an inductor and a variable capacitor and a switched capacitor array connected in parallel with the variable capacitor. The switched capacitor array further comprises a plurality of capacitor banks wherein a thermometer code is employed to control each capacitor bank. In addition, the switched capacitor array provides N tuning steps for the oscillation frequency of the voltage controlled oscillator when the switched capacitor array is controlled by an n-bit thermometer code.

    Abstract translation: 一种系统包括压控振荡器，其包括电感器和可变电容器以及与可变电容器并联连接的开关电容器阵列。 开关电容器阵列还包括多个电容器组，其中使用温度计代码来控制每个电容器组。 此外，当开关电容器阵列由n位温度计代码控制时，开关电容器阵列为压控振荡器的振荡频率提供N个调谐步骤。

    ESD BLOCK ISOLATION BY RF CHOKE
    8.
    发明申请
    ESD BLOCK ISOLATION BY RF CHOKE 有权
    防静电块隔离由RF CHOKE

    公开(公告)号：US20120212865A1

    公开(公告)日：2012-08-23

    申请号：US13029240

    申请日：2011-02-17

    Applicant: Ming Hsien TSAI ,  Jun-De JIN ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH

    Inventor： Ming Hsien TSAI ,  Jun-De JIN ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH

    IPC: H02H9/00

    CPC classification number: H01L27/0288 ,  H02H9/046

    Abstract: A circuit includes a first node configured to receive a radio frequency (“RF”) signal, a first electrostatic discharge (ESD) protection circuit coupled to a first voltage supply rail for an RF circuit and to a second node, and a second ESD protection circuit coupled to the second node and to a second voltage supply node for the RF circuit. An RF choke circuit is coupled to the second node and to a third node disposed between the first node and the RF circuit.

    Abstract translation: 电路包括被配置为接收射频（“RF”）信号的第一节点，耦合到用于RF电路的第一电压供电轨和第二节点的第一静电放电（ESD）保护电路，以及第二ESD保护 耦合到第二节点的电路和用于RF电路的第二电压供应节点。 RF扼流电路耦合到第二节点和设置在第一节点和RF电路之间的第三节点。

    MILLIMETER-WAVE WIDEBAND FREQUENCY DOUBLER
    10.
    发明申请
    MILLIMETER-WAVE WIDEBAND FREQUENCY DOUBLER 有权
    MILLIMETER-WAVE WIDEBAND频率双打

    公开(公告)号：US20120146747A1

    公开(公告)日：2012-06-14

    申请号：US12967160

    申请日：2010-12-14

    Applicant: Po-Yi WU ,  Hsieh-Hung HSIEH ,  Ho-Hsiang CHEN ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    Inventor： Po-Yi WU ,  Hsieh-Hung HSIEH ,  Ho-Hsiang CHEN ,  Tzu-Jin YEH ,  Chewn-Pu JOU ,  Fu-Lung HSUEH

    IPC: H03B19/00

    CPC classification number: H03B19/00

    Abstract: A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.

    Abstract translation: 用于分布式倍频器的毫米波宽带倍频器级包括：差分输入对晶体管，每个晶体管具有相应的栅极，漏极和源极端子，其中源极端子耦合到第一电源节点，并且 漏极端子在第一节点耦合到第二电源节点; 耦合到晶体管的栅极端子的第一和第二对带通栅极线; 以及耦合到晶体管的漏极端子的一对带通漏极线。

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