公开(公告)号：US5474958A

公开(公告)日：1995-12-12

申请号：US055863

申请日：1993-05-04

申请人： Frank Djennas ,  Victor K. Nomi ,  John R. Pastore ,  Twila J. Reeves ,  Les Postlethwait

发明人： Frank Djennas ,  Victor K. Nomi ,  John R. Pastore ,  Twila J. Reeves ,  Les Postlethwait

IPC分类号： B29C45/14 ,  B29L31/34 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L21/568 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/78743 ,  H01L2224/85001 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  Y10T29/49121 ,  Y10T29/49146 ,  Y10T29/49172

摘要： A wire bondable plastic encapsulated semiconductor device (58) having no die supporting surface can be manufactured. In one embodiment, a semiconductor die (22) and a plurality of conductors (12) extending toward the periphery of the die are provided. The die is rigidly held in place on a workholder (60) with a vacuum (62) for the wire bonding process. Wire bonds (26) electrically connect the die to the conductors. The wire bonded die is then placed inside a mold cavity (64), and a resin encapsulated is transferred into the cavity under elevated temperature and pressure to form package body (70) around the die, the wire bonds and a portion of the conductors. Before the package body is formed, the die is supported solely by the the rigidity of the wire bonds since there is no die supporting surface connected to the conductors.

摘要翻译： 可以制造不具有模具支撑表面的可焊线塑料封装半导体器件（58）。 在一个实施例中，提供半导体管芯（22）和朝向管芯周边延伸的多个导体（12）。 模具被刚性地保持在具有用于引线接合过程的真空（62）的工件架（60）上的适当位置。 引线键（26）将管芯与导体电连接。 然后将引线接合模具放置在模具腔（64）内，并且在升高的温度和压力下将封装的树脂转移到空腔中以在模具周围形成封装体（70），引线键合和一部分导体。 在封装体形成之前，由于没有与导体连接的模具支撑表面，所以模具仅由引线接合的刚性支撑。

公开(公告)号：USRE36773E

公开(公告)日：2000-07-11

申请号：US970272

申请日：1997-11-14

申请人： Victor K. Nomi ,  John R. Pastore ,  Twila J. Reeves

发明人： Victor K. Nomi ,  John R. Pastore ,  Twila J. Reeves

IPC分类号： H01L21/58 ,  H01L23/31 ,  H01L23/498 ,  H05K3/00 ,  H05K3/24 ,  H05K7/02

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/241 ,  Y10T29/49144

摘要： Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

摘要翻译： 通过提供作为外部电镀总线（16）的补充的嵌套电镀母线（18）来增加布线衬底（10）的布线密度。 第一组导电迹线（14）连接到嵌套电镀母线，而另一组导线连接到外部电镀母线。 在导电元件被电镀之后，通过蚀刻，铣削或冲压技术去除嵌套电镀母线。 嵌套电镀母线的使用增加给定衬底区域的I / O计数和/或减少在多于一层衬底上布线的需要。

公开(公告)号：US5467252A

公开(公告)日：1995-11-14

申请号：US136845

申请日：1993-10-18

申请人： Victor Nomi ,  John R. Pastore ,  Twila J. Reeves

发明人： Victor Nomi ,  John R. Pastore ,  Twila J. Reeves

IPC分类号： H01L21/58 ,  H01L23/31 ,  H01L23/498 ,  H05K3/00 ,  H05K3/24 ,  H05K7/02

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/241 ,  Y10T29/49144

摘要： Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.