公开(公告)号：US08283208B2

公开(公告)日：2012-10-09

申请号：US11813032

申请日：2005-12-28

申请人： Mitsumasa Koyanagi

发明人： Mitsumasa Koyanagi

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68313 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/75 ,  H01L2224/7598 ,  H01L2224/78743 ,  H01L2224/81097 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/81907 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2224/83907 ,  H01L2224/95001 ,  H01L2224/95145 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01031

摘要： In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of water films 81. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.

摘要翻译： 在制造具有三维堆叠结构的集成电路器件的方法中，可以以期望的精度容易且有效地执行将许多芯片形半导体电路固定到支撑衬底或具有预定布局的电路层的步骤。 半导体芯片13的临时粘合部分12b通过水膜81临时粘附到载体基板73a的相应的临时粘合区域72a上。然后将载体基板73a压向支撑基板或所需的电路层，从而接触连接部分 载体基板73a上的芯片13的12个，在支撑基板或电路层上具有对应的预定位置。 此后，通过将连接部分12固定到预定位置，芯片13以期望的布局附接到支撑基板或电路层。

公开(公告)号：US07998795B2

公开(公告)日：2011-08-16

申请号：US12817832

申请日：2010-06-17

申请人： Fujio Ito ,  Hiromichi Suzuki ,  Akihiko Kameoka ,  Noriaki Sakamoto

发明人： Fujio Ito ,  Hiromichi Suzuki ,  Akihiko Kameoka ,  Noriaki Sakamoto

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L24/85 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/06153 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/78743 ,  H01L2224/85148 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.

摘要翻译： 一种制造半导体器件的方法，包括将第一芯片安装在引线框架的芯片安装部分的第一区域上，并将第二芯片安装在芯片安装部分的第二区域上，其中第二区域与第一区域相邻 通过狭缝。 芯片安装部分设置在平坦的加热夹具上。 第一芯片的第一焊盘分别经由第一焊盘与第二焊盘的第二焊盘连接，并且第一焊盘分别经由第二焊盘与引线框架的引线连接。 第一芯片，第二芯片，第一线和第二线被树脂密封，使得每个引线的一部分从树脂露出，并且每个引线然后与引线框架分离。

公开(公告)号：US07772044B2

公开(公告)日：2010-08-10

申请号：US12263696

申请日：2008-11-03

申请人： Fujio Ito ,  Hiromichi Suzuki ,  Akihiko Kameoka ,  Noriaki Sakamoto

发明人： Fujio Ito ,  Hiromichi Suzuki ,  Akihiko Kameoka ,  Noriaki Sakamoto

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L24/85 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/06153 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/78743 ,  H01L2224/85148 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.

摘要翻译： 一种制造半导体器件的方法，包括将第一芯片安装在引线框架的芯片安装部分的第一区域上，并将第二芯片安装在芯片安装部分的第二区域上，其中第二区域与第一区域相邻 通过狭缝。 芯片安装部分设置在平坦的加热夹具上。 第一芯片的第一焊盘分别经由第一焊盘与第二焊盘的第二焊盘连接，并且第一焊盘分别经由第二焊盘与引线框架的引线连接。 第一芯片，第二芯片，第一线和第二线被树脂密封，使得每个引线的一部分从树脂露出，并且每个引线然后与引线框架分离。

公开(公告)号：US20090061563A1

公开(公告)日：2009-03-05

申请号：US12263696

申请日：2008-11-03

申请人： Fujio ITO ,  Hiromichi SUZUKI ,  Akihiko KAMEOKA ,  Noriaki SAKAMOTO

发明人： Fujio ITO ,  Hiromichi SUZUKI ,  Akihiko KAMEOKA ,  Noriaki SAKAMOTO

IPC分类号： H01L21/50

CPC分类号： H01L24/85 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/06153 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/78743 ,  H01L2224/85148 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for manufacturing a semiconductor device includes mounting a first chip over a first area of a chip mounting section of a lead frame and mounting a second chip over a second area of the chip mounting section, wherein the second area is adjacent to the first area via the slit. The chip mounting section is disposed on a flat heating jig. First pads of the first chip are connected with second pads of the second chip via first wires, respectively, and the first pads are connected with leads of the lead frame via second wires, respectively. the first chip, the second chip, the first wires and the second wires are sealed with a resin such that a part of each of the leads is exposed from the resin, and each of the leads is then separated from the lead frame.

摘要翻译： 一种制造半导体器件的方法，包括将第一芯片安装在引线框架的芯片安装部分的第一区域上，并将第二芯片安装在芯片安装部分的第二区域上，其中第二区域与第一区域相邻 通过狭缝。 芯片安装部分设置在平坦的加热夹具上。 第一芯片的第一焊盘分别经由第一焊盘与第二焊盘的第二焊盘连接，并且第一焊盘分别经由第二焊盘与引线框架的引线连接。 第一芯片，第二芯片，第一线和第二线被树脂密封，使得每个引线的一部分从树脂露出，并且每个引线然后与引线框架分离。

公开(公告)号：US20080277149A1

公开(公告)日：2008-11-13

申请号：US11831086

申请日：2007-07-31

申请人： Shingo KURODA

发明人： Shingo KURODA

IPC分类号： H05K1/16 ,  H05K3/00

CPC分类号： H01L24/86 ,  H01L23/49572 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/50 ,  H01L24/80 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/50 ,  H01L2224/78301 ,  H01L2224/78743 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/53191 ,  Y10T29/53261 ,  Y10T29/53265 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing an electronic device includes: preparing an electronic component having an electrode; fixing the electronic component to a supporter, the supporter having a support surface and an inlet disposed in a position that is at a side of the support surface and lower than the support surface, by supporting the electronic component with the support surface so that the electronic component does not come into contact with the inlet and so that a part of a surface of the electronic component adjacent to the support surface is exposed out of the support surface and by attracting a region of the electronic component exposed out of the support surface toward the inlet; and electrically coupling the electrode and a conductive pattern with the electronic component fixed to the supporter.

摘要翻译： 一种电子设备的制造方法，包括：准备具有电极的电子部件; 将所述电子部件固定在支撑体上，所述支撑体具有支撑面和设置在所述支撑面的一侧且比所述支撑面低的位置的入口，通过将所述电子部件支撑在所述支撑面上，使得所述电子部件 部件不与入口接触，使得与支撑表面相邻的电子部件的表面的一部分暴露在支撑表面之外，并且通过将从支撑表面露出的电子部件的区域吸引到 进口; 并且将电极和导电图案电耦合到固定到支撑件的电子部件。

公开(公告)号：US20070035017A1

公开(公告)日：2007-02-15

申请号：US11580904

申请日：2006-10-16

申请人： Fujio Ito ,  Hiromichi Suzuki ,  Akihiko Kameoka ,  Noriaki Sakamoto

发明人： Fujio Ito ,  Hiromichi Suzuki ,  Akihiko Kameoka ,  Noriaki Sakamoto

IPC分类号： H01L23/34 ,  H01L21/00

CPC分类号： H01L24/85 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/06153 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/78743 ,  H01L2224/85148 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.

摘要翻译： 半导体器件包括微计算机芯片，与微计算机芯片一起设置并且比微计算机芯片薄的SDRAM，多个内引线和外引线，连接微计算机芯片的焊盘和第二引线的第一引线 SDRAM和第二线，其连接微型计算机芯片的焊盘和内部引线，并布置成跨越SDRAM并且在高于第一线的环的位置处形成有环。 用于存储器总线的接口电路仅在芯片之间连接，而不连接到外部端子，并且在封装内封闭。 因此，可以相应地使用引脚用于其他功能，并且可以实现多引脚配置。 此外，由于采用帧类型，可以降低SIP（半导体器件）的成本。

公开(公告)号：US20010054640A1

公开(公告)日：2001-12-27

申请号：US09932947

申请日：2001-08-21

发明人： Yoshiharu Takahashi

IPC分类号： B23K031/02

CPC分类号： H01L24/85 ,  H01L23/49503 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78251 ,  H01L2224/78703 ,  H01L2224/78743 ,  H01L2224/85045 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A wire bonding apparatus for a semiconductor device comprising a semiconductor chip, and a lead frame having a die pad to which the semiconductor chip is joined and a plurality of inner leads which are aligned along a periphery of the die pad at specified intervals. The apparatus includes a heat block having an inner lead mounting portion for mounting the inner leads, a concave portion provided inward of the inner lead mounting portion and at least one supporting pad for mounting the semiconductor chip. Influences of restoration of the lead frame on wire bonding portions can be decreased at the time the lead frame forcing means is detached.

摘要翻译： 一种用于半导体器件的引线接合装置，包括半导体芯片和具有半导体芯片接合的管芯焊盘的引线框架和以规定间隔沿着管芯焊盘的周边排列的多个内部引线。 该装置包括具有用于安装内引线的内引线安装部分，设置在内引线安装部分内侧的凹部和用于安装半导体芯片的至少一个支撑焊盘的加热块。 在引线框架强制装置脱离时，可以减少引线框架对引线接合部分的恢复的影响。

公开(公告)号：US08439249B2

公开(公告)日：2013-05-14

申请号：US12567434

申请日：2009-09-25

申请人： Roland Speckels ,  Thomas Licht ,  Karsten Guth

发明人： Roland Speckels ,  Thomas Licht ,  Karsten Guth

IPC分类号： B23K20/08 ,  H01L21/00

CPC分类号： H01L21/67092 ,  H01L21/6835 ,  H01L23/3735 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/93 ,  H01L25/072 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/78743 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/01028

摘要： A device and a method for making a semiconductor device including bonding a first bonding partner to a second bonding partner. The device comprises a lower tool and an upper tool, the upper tool including a plunger having a bottom side facing the lower tool at which bottom side a vacuum is creatable, so that the first bonding partner can be picked up by vacuum from the upper tool and positioned on the second bonding partner.

摘要翻译： 一种用于制造半导体器件的器件和方法，包括将第一结合伙伴接合到第二接合伙伴。 所述装置包括下部工具和上部工具，所述上部工具包括柱塞，所述柱塞具有面向所述下部工具的底侧，在所述下部工具的下侧可创建真空，从而可以从所述上部工具通过真空拾取所述第一焊接对象 并且位于第二粘合伙伴上。

公开(公告)号：US20110249113A1

公开(公告)日：2011-10-13

申请号：US13151083

申请日：2011-06-01

申请人： Mitsumasa KOYANAGI

发明人： Mitsumasa KOYANAGI

IPC分类号： H04N7/18 ,  B32B37/00

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/13 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68313 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/75 ,  H01L2224/7598 ,  H01L2224/78743 ,  H01L2224/81097 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/81907 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2224/83907 ,  H01L2224/95001 ,  H01L2224/95145 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01031

摘要： In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of water films 81. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.

摘要翻译： 在制造具有三维堆叠结构的集成电路器件的方法中，可以以期望的精度容易且有效地执行将许多芯片形半导体电路固定到支撑衬底或具有预定布局的电路层的步骤。 半导体芯片13的临时粘合部分12b通过水膜81临时粘附到载体基板73a的相应的临时粘合区域72a上。然后将载体基板73a压向支撑基板或所需的电路层，从而接触连接部分 载体基板73a上的芯片13的12个，在支撑基板或电路层上具有对应的预定位置。 此后，通过将连接部分12固定到预定位置，芯片13以期望的布局附接到支撑基板或电路层。

公开(公告)号：US20090309211A1

公开(公告)日：2009-12-17

申请号：US12543358

申请日：2009-08-18

申请人： Jeffrey W. Marsh ,  R. Tracy White ,  David L. Hamilton

发明人： Jeffrey W. Marsh ,  R. Tracy White ,  David L. Hamilton

IPC分类号： H01L23/488

CPC分类号： H01L24/78 ,  B23K20/004 ,  B23K2101/40 ,  H01L21/6835 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/78301 ,  H01L2224/78743 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/3011 ,  Y10S228/904 ,  Y10S269/903 ,  Y10T29/53174 ,  H01L2224/48 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015

摘要： A wire bonder (900) with a rigid pedestal (902) having resilient inserts (920). A package (904) placed on the pedestal (902) contains an electrical device (906). The bond pads on the electrical device (906) are electrically connected to bond pads on the package (904) by a series of bond wires (908) through use of a well know bonding process. A vacuum source holds the package (904) against the pedestal (902) deforming the resilient strips (920) located in the rigid member (902) of the pedestal and ensuring good contact between the ground pads of the package (904) and conductive resilient members (920). The resilient members (920) are conductive and electrically connect the package grounds to a system ground (922).

摘要翻译： 具有刚性基座（902）的引线接合器（900）具有弹性插入件（920）。 放置在基座（902）上的包装（904）包含电气装置（906）。 电气设备（906）上的接合焊盘通过使用众所周知的接合工艺通过一系列接合线（908）电连接到封装（904）上的接合焊盘。 真空源将包装（904）保持抵靠基座（902）使位于基座的刚性构件（902）中的弹性条（920）变形，并确保封装（904）的接地焊盘与导电弹性 会员（920）。 弹性构件（920）是导电的并将封装接地电连接到系统接地（922）。