公开(公告)号：US5474958A

公开(公告)日：1995-12-12

申请号：US055863

申请日：1993-05-04

申请人： Frank Djennas ,  Victor K. Nomi ,  John R. Pastore ,  Twila J. Reeves ,  Les Postlethwait

发明人： Frank Djennas ,  Victor K. Nomi ,  John R. Pastore ,  Twila J. Reeves ,  Les Postlethwait

IPC分类号： B29C45/14 ,  B29L31/34 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L21/568 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/78743 ,  H01L2224/85001 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01014 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  Y10T29/49121 ,  Y10T29/49146 ,  Y10T29/49172

摘要： A wire bondable plastic encapsulated semiconductor device (58) having no die supporting surface can be manufactured. In one embodiment, a semiconductor die (22) and a plurality of conductors (12) extending toward the periphery of the die are provided. The die is rigidly held in place on a workholder (60) with a vacuum (62) for the wire bonding process. Wire bonds (26) electrically connect the die to the conductors. The wire bonded die is then placed inside a mold cavity (64), and a resin encapsulated is transferred into the cavity under elevated temperature and pressure to form package body (70) around the die, the wire bonds and a portion of the conductors. Before the package body is formed, the die is supported solely by the the rigidity of the wire bonds since there is no die supporting surface connected to the conductors.

摘要翻译： 可以制造不具有模具支撑表面的可焊线塑料封装半导体器件（58）。 在一个实施例中，提供半导体管芯（22）和朝向管芯周边延伸的多个导体（12）。 模具被刚性地保持在具有用于引线接合过程的真空（62）的工件架（60）上的适当位置。 引线键（26）将管芯与导体电连接。 然后将引线接合模具放置在模具腔（64）内，并且在升高的温度和压力下将封装的树脂转移到空腔中以在模具周围形成封装体（70），引线键合和一部分导体。 在封装体形成之前，由于没有与导体连接的模具支撑表面，所以模具仅由引线接合的刚性支撑。

公开(公告)号：USRE36773E

公开(公告)日：2000-07-11

申请号：US970272

申请日：1997-11-14

申请人： Victor K. Nomi ,  John R. Pastore ,  Twila J. Reeves

发明人： Victor K. Nomi ,  John R. Pastore ,  Twila J. Reeves

IPC分类号： H01L21/58 ,  H01L23/31 ,  H01L23/498 ,  H05K3/00 ,  H05K3/24 ,  H05K7/02

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/241 ,  Y10T29/49144

摘要： Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

摘要翻译： 通过提供作为外部电镀总线（16）的补充的嵌套电镀母线（18）来增加布线衬底（10）的布线密度。 第一组导电迹线（14）连接到嵌套电镀母线，而另一组导线连接到外部电镀母线。 在导电元件被电镀之后，通过蚀刻，铣削或冲压技术去除嵌套电镀母线。 嵌套电镀母线的使用增加给定衬底区域的I / O计数和/或减少在多于一层衬底上布线的需要。

公开(公告)号：US5467252A

公开(公告)日：1995-11-14

申请号：US136845

申请日：1993-10-18

申请人： Victor Nomi ,  John R. Pastore ,  Twila J. Reeves

发明人： Victor Nomi ,  John R. Pastore ,  Twila J. Reeves

IPC分类号： H01L21/58 ,  H01L23/31 ,  H01L23/498 ,  H05K3/00 ,  H05K3/24 ,  H05K7/02

CPC分类号： H01L24/32 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/241 ,  Y10T29/49144

摘要： Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

公开(公告)号：US5731709A

公开(公告)日：1998-03-24

申请号：US592256

申请日：1996-01-26

申请人： John R. Pastore ,  Victor K. Nomi ,  Howard P. Wilson

发明人： John R. Pastore ,  Victor K. Nomi ,  Howard P. Wilson

IPC分类号： G01R1/04 ,  G01R31/02

CPC分类号： G01R1/0483 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/73 ,  H01L2924/01322 ,  H01L2924/15311

摘要： A ball grid array semiconductor device (30) includes a plurality of conductive balls (36) and a plurality of conductive castellations (18) around its periphery as redundant electrical connections to a semiconductor die (12). During testing of the device in a test socket (50), the conductive castellations are contacted by test contacts (54). The test contacts do not come in physical contact with the conductive balls. As a result, when testing is performed at elevated temperatures near the melting point of the conductive balls, the conductive balls are not deformed by the test contacts, thereby eliminating cosmetic-defects. Additionally, the absence of physical contact between the conductive balls and the test contacts during testing reduces the likelihood that conductive balls will inadvertently fuse to the test socket or create solder build-up on the test contacts.

摘要翻译： 球栅阵列半导体器件（30）包括围绕其周边的多个导电球（36）和多个导电堰（18），作为到半导体管芯（12）的冗余电连接。 在测试插座（50）中测试设备期间，导电蓖耳体被测试触点（54）接触。 测试触点不会与导电球物理接触。 结果，当在导电球的熔点附近的高温下进行测试时，导电球不会被测试触点变形，从而消除了美观缺陷。 另外，在测试期间导电球和测试触点之间不存在物理接触会降低导电球将不经意地融合到测试插座或在测试触点上产生焊料积聚的可能性。

公开(公告)号：US5691242A

公开(公告)日：1997-11-25

申请号：US606981

申请日：1996-02-26

申请人： Victor K. Nomi ,  John R. Pastore ,  Charles G. Bigler

发明人： Victor K. Nomi ,  John R. Pastore ,  Charles G. Bigler

IPC分类号： H01L23/04 ,  H01L23/13 ,  H01L23/31 ,  H01L23/544 ,  H01L21/60

CPC分类号： H01L23/544 ,  H01L23/13 ,  H01L23/3121 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181

摘要： A method for packaging an integrated circuit begins by providing an organic substrate (310) having at least one device site (312). Within each device site, one or more electronic devices (532) is mounted. Around the device site, slots (316) and corner holes (318) are formed. In one embodiment, a negative feature, such as a notch (326), is formed in the substrate along the inner edge (315) of the slots. After the electronic device is mounted and encapsulated in a plastic package body (320), the device is excised from the substrate by punching corner regions of a final package perimeter (317). The placement of the slots, corner holes, and notches results in a punch periphery that is free from burrs, provides maximum active interconnect area, and minimizes surface and/or edge damage during the punch operation. Instead of forming notches, a positive feature, such as a protrusion (426) can be incorporated into a punching tool segment (428) to provide the same benefits.

摘要翻译： 一种用于封装集成电路的方法通过提供具有至少一个器件位置（312）的有机衬底（310）开始。 在每个设备站点内安装一个或多个电子设备（532）。 围绕设备现场，形成槽（316）和角孔（318）。 在一个实施例中，沿着槽的内边缘（315）在衬底中形成负特征，例如凹口（326）。 在将电子设备安装并封装在塑料封装主体（320）中之后，通过冲压最终封装周边（317）的拐角区域将装置从基板上排出。 槽，角孔和缺口的放置导致没有毛刺的冲头周边，提供最大的有源互连面积，并且在冲压操作期间最小化表面和/或边缘损伤。 代替形成凹口，可以将诸如突起（426）的积极特征结合到冲压工具段（428）中以提供相同的益处。

公开(公告)号：US5285352A

公开(公告)日：1994-02-08

申请号：US913312

申请日：1992-07-15

申请人： John R. Pastore ,  Victor K. Nomi ,  Howard P. Wilson

发明人： John R. Pastore ,  Victor K. Nomi ,  Howard P. Wilson

IPC分类号： H01L23/12 ,  H01L23/36 ,  H01L23/367 ,  H05K7/20

CPC分类号： H01L23/36 ,  H01L23/3677 ,  H01L2224/32013 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107

摘要： A pad array semiconductor device (35) includes a thermal conductor (28) integrated into a circuitized substrate (14). A semiconductor die (12) is mounted on the substrate overlying the thermal conductor to establish a thermal path away from the die. The thermal conductor may also be covered or surrounded by a metallized area (37, 39), which together may serve as a ground plane in the device. Preferably one or more terminals (26) are attached to the thermal conductor for improved thermal and electrical performance. One method of integrating the thermal conductor in the substrate is to position a metal plug into an opening 30 of the substrate. The plug is then compressed or otherwise plastically deformed to fill the opening and create a substantially planar substrate surface.

摘要翻译： 焊盘阵列半导体器件（35）包括集成到电路化衬底（14）中的热导体（28）。 半导体管芯（12）安装在覆盖导热体的衬底上，以建立远离管芯的热路径。 热导体也可以被金属化区域（37,39）覆盖或围绕，金属化区域可一起用作设备中的接地平面。 优选地，一个或多个端子（26）附接到热导体以改善热和电性能。 将热导体集成在基板中的一种方法是将金属塞定位到基板的开口30中。 然后塞子被压缩或以其他方式塑性变形以填充开口并产生基本平坦的基板表面。

公开(公告)号：US5287962A

公开(公告)日：1994-02-22

申请号：US933541

申请日：1992-08-24

申请人： Victor K. Nomi ,  John R. Pastore

发明人： Victor K. Nomi ,  John R. Pastore

IPC分类号： B65D81/20 ,  H01L21/673 ,  B65D73/02

CPC分类号： B65D81/203 ,  Y10S206/807 ,  Y10S428/916

摘要： Plastic encapsulated semiconductor devices are susceptible to moisture due to the permeability of molding compounds. Devices may be baked until dry before being shipped to the customer to reduce the risk of cracking. To retain this dry condition, devices are packaged and shipped in dry-packs. A vacuum seal indicator (18) for flexible material enables a user to determine the integrity of a vacuum seal. The seal indicator has a quick recognition pattern composed of either negative (22) or positive (24) features or a combination thereof, and is placed inside a dry-pack bag (30) which is vacuum sealed prior to shipping. The integrity of the vacuum seal can be determined by looking at the dry-pack bag to see whether the recognition pattern is sharply defined against the bag or not. The vacuum seal indicator can be used in conjunction with any shipping media (28) as long as the outer bag is flexible.

摘要翻译： 由于模塑料的渗透性，塑料封装的半导体器件易受潮湿。 设备可以在运输到客户之前烘烤直到干燥，以降低开裂的风险。 为了保持这种干燥条件，设备被包装并以干包装运输。 用于柔性材料的真空密封指示器（18）使得用户能够确定真空密封的完整性。 密封指示器具有由负（22）或正（24）特征或其组合组成的快速识别图案，并且放置在运输之前被真空密封的干包装袋（30）内。 可以通过观察干包袋来确定真空密封件的完整性，以查看识别图案是否相对于袋子被清晰地定义。 真空密封指示器可以与任何运输介质（28）一起使用，只要外袋是柔性的。