-
公开(公告)号：US20140281133A1
公开(公告)日：2014-09-18
申请号：US13838699
申请日：2013-03-15
IPC分类号： G06F12/02
CPC分类号： G06F3/061 , G06F3/0611 , G06F3/0655 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F9/4881 , G06F9/5016 , G06F12/0246 , G06F2212/7206 , G06F2212/7208
摘要： Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.
摘要翻译： 一些实施方案包括管理基于非易失性随机存取存储器（NVRAM）的存储子系统的方法，该存储子系统包括NVRAM器件。 该方法包括：在主机计算设备上的设备驱动器处，接收每个请求将相应的数据单元写入到基于NVRAM的存储子系统的请求; 将写请求分类为写请求的子组，其中各子组内的写请求是相互排斥的; 确定基于NVRAM的存储子系统的几个NVRAM设备中的每一个的负载状况; 根据所确定的基于NVRAM的存储子系统的NVRAM设备的负载条件，在至少一个NVRAM设备上识别目标位置来服务特定的写请求子组; 以及通过将相应的数据单元写入到基于NVRAM的存储子系统的至少一个NVRAM设备上的所识别的目标位置来为特定的写请求组提供服务。
-
2.发明授权公开(公告)号：US08949555B1
公开(公告)日：2015-02-03
申请号：US13162575
申请日：2011-06-16
申请人： Vijay Karamcheti , Shibabrata Mondal , Ajith Kumar
发明人： Vijay Karamcheti , Shibabrata Mondal , Ajith Kumar
IPC分类号： G06F12/00
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F12/0253 , G06F12/06 , G06F13/161 , G06F13/1626 , G06F13/1642 , G06F13/1657 , G06F13/1694 , G06F13/18 , G06F13/364 , G06F13/4081 , G06F13/4282 , G06F2212/25 , G06F2212/702 , G06F2212/7203 , G06F2212/7205
摘要： In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.
摘要翻译： 在本发明的一个实施例中，存储器系统包括耦合到存储器通道以共享总线的非易失性存储器件（NVMD）和耦合到多个NVMD之间的通信中的存储器通道的存储器控制器。 每个NVMD一次独立地执行读，写或擦除操作。 存储器控制器包括用于调度与存储器通道上的读取，写入和擦除操作相关联的控制和数据传输的信道调度器; 以及耦合到信道调度器的高优先级和低优先级队列。 信道调度器优先处理在高优先级队列中等待低优先级队列中的操作的操作。 信道调度器进一步优先考虑在高优先级队列或低优先级队列中等待在每个相应队列中等待的写入和擦除操作的读取操作。
-
3.发明授权公开(公告)号：US08341300B1
公开(公告)日：2012-12-25
申请号：US13162572
申请日：2011-06-16
申请人： Vijay Karamcheti , Shibabrata Mondal , Ajith Kumar
发明人： Vijay Karamcheti , Shibabrata Mondal , Ajith Kumar
CPC分类号： G06F13/1684 , G06F13/1642 , Y02D10/14
摘要： In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.
摘要翻译： 在本发明的一个实施例中，存储器系统包括耦合到存储器通道以共享总线的非易失性存储器件（NVMD）和耦合到多个NVMD之间的通信中的存储器通道的存储器控制器。 每个NVMD一次独立地执行读，写或擦除操作。 存储器控制器包括用于调度与存储器通道上的读取，写入和擦除操作相关联的控制和数据传输的信道调度器; 以及耦合到信道调度器的高优先级和低优先级队列。 信道调度器优先处理在高优先级队列中等待低优先级队列中的操作的操作。 信道调度器进一步优先考虑在高优先级队列或低优先级队列中等待在每个相应队列中等待的写入和擦除操作的读取操作。
-
公开(公告)号：US20140281138A1
公开(公告)日：2014-09-18
申请号：US13842079
申请日：2013-03-15
申请人： Vijay Karamcheti , Shibabrata Mondal , Swamy Gowda
发明人： Vijay Karamcheti , Shibabrata Mondal , Swamy Gowda
IPC分类号： G06F12/02
CPC分类号： G06F11/2058 , G06F11/14 , G06F11/1451 , G06F11/2082 , G06F12/0246 , G06F2201/84 , G06F2212/7201 , G06F2212/7202
摘要： First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.
摘要翻译： 接收第一数据以存储在第一非对称存储器件中。 第一个写入阶段被识别为当前写入阶段。 包括在第一非对称存储器件中的第一段被识别为可用于写入数据的下一段。 第一个数据被写入第一个数据段。 存储与第一段相关联的信息，以及指示第一段被写入第一写入阶段的信息。 接收第二数据以存储在非对称存储器中。 包括在第一非对称存储器件中的第二段被识别为可用于写入数据的下一段。 第二个数据被写入第二个数据段。 与第二段和第二存储块相关联的信息与指示第二段被写入第二写入阶段的信息一起被存储。
-
-
-
搜索结果
4 条记录 (耗时 0.019 秒)
