公开(公告)号：US20140281138A1

公开(公告)日：2014-09-18

申请号：US13842079

申请日：2013-03-15

申请人： Vijay Karamcheti ,  Shibabrata Mondal ,  Swamy Gowda

发明人： Vijay Karamcheti ,  Shibabrata Mondal ,  Swamy Gowda

IPC分类号： G06F12/02

CPC分类号： G06F11/2058 ,  G06F11/14 ,  G06F11/1451 ,  G06F11/2082 ,  G06F12/0246 ,  G06F2201/84 ,  G06F2212/7201 ,  G06F2212/7202

摘要： First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.

摘要翻译： 接收第一数据以存储在第一非对称存储器件中。 第一个写入阶段被识别为当前写入阶段。 包括在第一非对称存储器件中的第一段被识别为可用于写入数据的下一段。 第一个数据被写入第一个数据段。 存储与第一段相关联的信息，以及指示第一段被写入第一写入阶段的信息。 接收第二数据以存储在非对称存储器中。 包括在第一非对称存储器件中的第二段被识别为可用于写入数据的下一段。 第二个数据被写入第二个数据段。 与第二段和第二存储块相关联的信息与指示第二段被写入第二写入阶段的信息一起被存储。

公开(公告)号：US20140281133A1

公开(公告)日：2014-09-18

申请号：US13838699

申请日：2013-03-15

申请人： Vijay Karamcheti ,  Ashish Singhai ,  Shibabrata Mondal ,  Ajith Kumar

发明人： Vijay Karamcheti ,  Ashish Singhai ,  Shibabrata Mondal ,  Ajith Kumar

IPC分类号： G06F12/02

CPC分类号： G06F3/061 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0246 ,  G06F2212/7206 ,  G06F2212/7208

摘要： Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

摘要翻译： 一些实施方案包括管理基于非易失性随机存取存储器（NVRAM）的存储子系统的方法，该存储子系统包括NVRAM器件。 该方法包括：在主机计算设备上的设备驱动器处，接收每个请求将相应的数据单元写入到基于NVRAM的存储子系统的请求; 将写请求分类为写请求的子组，其中各子组内的写请求是相互排斥的; 确定基于NVRAM的存储子系统的几个NVRAM设备中的每一个的负载状况; 根据所确定的基于NVRAM的存储子系统的NVRAM设备的负载条件，在至少一个NVRAM设备上识别目标位置来服务特定的写请求子组; 以及通过将相应的数据单元写入到基于NVRAM的存储子系统的至少一个NVRAM设备上的所识别的目标位置来为特定的写请求组提供服务。

公开(公告)号：US08949555B1

公开(公告)日：2015-02-03

申请号：US13162575

申请日：2011-06-16

申请人： Vijay Karamcheti ,  Shibabrata Mondal ,  Ajith Kumar

发明人： Vijay Karamcheti ,  Shibabrata Mondal ,  Ajith Kumar

IPC分类号： G06F12/00

CPC分类号： G06F3/061 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/06 ,  G06F13/161 ,  G06F13/1626 ,  G06F13/1642 ,  G06F13/1657 ,  G06F13/1694 ,  G06F13/18 ,  G06F13/364 ,  G06F13/4081 ,  G06F13/4282 ,  G06F2212/25 ,  G06F2212/702 ,  G06F2212/7203 ,  G06F2212/7205

摘要： In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.

摘要翻译： 在本发明的一个实施例中，存储器系统包括耦合到存储器通道以共享总线的非易失性存储器件（NVMD）和耦合到多个NVMD之间的通信中的存储器通道的存储器控​​制器。 每个NVMD一次独立地执行读，写或擦除操作。 存储器控制器包括用于调度与存储器通道上的读取，写入和擦除操作相关联的控制和数据传输的信道调度器; 以及耦合到信道调度器的高优先级和低优先级队列。 信道调度器优先处理在高优先级队列中等待低优先级队列中的操作的操作。 信道调度器进一步优先考虑在高优先级队列或低优先级队列中等待在每个相应队列中等待的写入和擦除操作的读取操作。

公开(公告)号：US08341300B1

公开(公告)日：2012-12-25

申请号：US13162572

申请日：2011-06-16

申请人： Vijay Karamcheti ,  Shibabrata Mondal ,  Ajith Kumar

发明人： Vijay Karamcheti ,  Shibabrata Mondal ,  Ajith Kumar

IPC分类号： G06F3/00 ,  G06F13/12

CPC分类号： G06F13/1684 ,  G06F13/1642 ,  Y02D10/14

摘要： In one embodiment of the invention, a memory system includes non-volatile-memory-devices (NVMDs) coupled to memory channels to share busses and a memory controller coupled to the memory channels in communication between the plurality of NVMDs. Each NVMD independently executes a read, write, or erase operation at a time. The memory controller includes channel schedulers to schedule control and data transfers associated with the read, write, and erase operations on the memory channels; and high priority and low priority queues coupled to the channel schedulers. The channel schedulers prioritize operations waiting in the high priority queues over operations waiting in the low priority queues. The channel schedulers further prioritize read operations waiting in either the high priority queue or the low priority queue over write and erase operations waiting in each respective queue.

摘要翻译： 在本发明的一个实施例中，存储器系统包括耦合到存储器通道以共享总线的非易失性存储器件（NVMD）和耦合到多个NVMD之间的通信中的存储器通道的存储器控​​制器。 每个NVMD一次独立地执行读，写或擦除操作。 存储器控制器包括用于调度与存储器通道上的读取，写入和擦除操作相关联的控制和数据传输的信道调度器; 以及耦合到信道调度器的高优先级和低优先级队列。 信道调度器优先处理在高优先级队列中等待低优先级队列中的操作的操作。 信道调度器进一步优先考虑在高优先级队列或低优先级队列中等待在每个相应队列中等待的写入和擦除操作的读取操作。

公开(公告)号：US08856464B2

公开(公告)日：2014-10-07

申请号：US12369728

申请日：2009-02-11

申请人： Vijay Karamcheti ,  Kumar Ganapathy

发明人： Vijay Karamcheti ,  Kumar Ganapathy

IPC分类号： G06F12/00 ,  G06F12/02 ,  G11C5/04 ,  G11C29/00

CPC分类号： G06F12/0246 ,  G11C5/04 ,  G11C29/76

摘要： In one embodiment of the invention, a system is disclosed including a master memory controller and a plurality of memory modules coupled to the master memory controller. Each memory module includes a plurality of read-writeable non-volatile memory devices in a plurality of memory slices to form a two-dimensional array of memory. Each memory slice in each memory module includes a slave memory controller coupled to the master memory controller. When the master memory controller issues a memory module request, it is partitioned into a slice request for each memory slice.

摘要翻译： 在本发明的一个实施例中，公开了一种包括主存储器控制器和耦合到主存储器控制器的多个存储器模块的系统。 每个存储器模块在多个存储器片中包括多个可读写非易失性存储器件，以形成二维存储器阵列。 每个存储器模块中的每个存储器片包括耦合到主存储器控制器的从存储器控制器。 当主存储器控制器发出存储器模块请求时，它被分割成每个存储器片的片请求。

公开(公告)号：US08850091B1

公开(公告)日：2014-09-30

申请号：US13745804

申请日：2013-01-20

申请人： Vijay Karamcheti ,  Ashwin Narasimha

发明人： Vijay Karamcheti ,  Ashwin Narasimha

IPC分类号： G06F13/12 ,  G06F12/02

CPC分类号： G06F1/30 ,  G06F1/266 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0685 ,  G06F11/3058 ,  G06F12/0246 ,  G06F2212/7208

摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.

摘要翻译： 在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。 存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。 每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。 响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。

公开(公告)号：US08516172B1

公开(公告)日：2013-08-20

申请号：US13163481

申请日：2011-06-17

申请人： Vijay Karamcheti ,  Ashwin Narasimha

发明人： Vijay Karamcheti ,  Ashwin Narasimha

IPC分类号： G06F13/12

CPC分类号： G06F1/30 ,  G06F1/266 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0685 ,  G06F11/3058 ,  G06F12/0246 ,  G06F2212/7208

摘要： In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.

摘要翻译： 在本发明的一个实施例中，公开了一种用于改善写入性能的存储装置。 存储装置包括具有用于插入主机服务器系统的边缘连接器的基底印刷电路板（PCB）; 在电源故障期间提供卡级电源的卡级电源; 存储器控制器，其耦合到所述卡级电源并具有一个或多个存储器通道; 以及耦合到卡级电源并被组织以分别耦合到由存储器控制器控制的存储器通道的一个或多个非易失性存储器件（NVMD）。 每个存储器控制器在存储器通道中的每个NVMD的通道上提供对存储器操作的排队和调度。 响应于电源故障，存储器控制器接收卡级电源，并将存储器操作的调度改变为每个存储器通道中的NVMD。

公开(公告)号：US08407439B2

公开(公告)日：2013-03-26

申请号：US13441663

申请日：2012-04-06

申请人： Kenneth A. Okin ,  Vijay Karamcheti

发明人： Kenneth A. Okin ,  Vijay Karamcheti

IPC分类号： G06F12/00

CPC分类号： G06F12/02 ,  G06F11/1658 ,  G06F11/20 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/08 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7202 ,  G11C16/3418 ,  G11C16/3427

摘要： A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

摘要翻译： 存储器控制器（MC）与重映射表相关联，以使得能够访问包括非对称存储器的存储器系统中的内容。 MC从系统的存储器管理单元（MMU）指定的物理地址从中央处理单元（CPU）接收对存储器读取或输入/输出（I / O）写入的请求。 通过将与CPU指令关联的虚拟地址转换为表示系统内存或I / O位置的物理地址，CPU使用MMU来管理CPU的存储器操作。 用于非对称存储器的MC被配置为处理MMU指定的物理地址作为附加类型的虚拟地址，在MMU指定的物理地址与该地址由MC关联的物理存储器地址之间创建一个抽象层 。 MC屏蔽CPU免受实现具有不对称组件的存储系统所需的计算复杂性。

公开(公告)号：US08364867B2

公开(公告)日：2013-01-29

申请号：US12831206

申请日：2010-07-06

申请人： Vijay Karamcheti ,  Kumar Ganapathy ,  Kenneth Alan Okin ,  Rajesh Parekh

发明人： Vijay Karamcheti ,  Kumar Ganapathy ,  Kenneth Alan Okin ,  Rajesh Parekh

IPC分类号： G06F13/12

CPC分类号： G06F13/1657 ,  Y02D10/14

摘要： A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces.The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.

摘要翻译： 公开了一种计算系统，其包括通常为处理器预留的处理器插座中的存储器控​​制器。 多个非易失性存储器模块可以插入通常保留给DRAM存储器模块的存储器插槽中。 可以使用数据通信协议访问非易失性存储器模块以访问非易失性存储器模块。 存储器控制器控制对非易失性存储器模块的读取和写入访问。 存储器插座通过印刷电路板迹线耦合到处理器插座。 用于访问非易失性存储器模块的数据通信协议通过印刷电路板迹线和通常用于访问DRAM型存储器模块的插槽来传送。

公开(公告)号：US20130007338A1

公开(公告)日：2013-01-03

申请号：US13608937

申请日：2012-09-10

申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

IPC分类号： G06F12/08

CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

摘要翻译： 存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。 计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性 写这个地址。 非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。