公开(公告)号：US06960819B2

公开(公告)日：2005-11-01

申请号：US09739752

申请日：2000-12-20

申请人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

发明人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

IPC分类号： G11C17/00 ,  G11C17/18 ,  H01L27/112 ,  H01L29/00

CPC分类号： G11C17/18 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current, and a switch having a voltage tolerance higher than that of the capacitor/transistor, wherein the capacitor/transistor is one-time programmable as an anti-fuse by application of a voltage across the oxide layer via the switch to cause direct gate tunneling current to thereby rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

摘要翻译： 一种能够以0.13μm或更低的CMOS技术制造的一次性编程存储器元件，具有可以通过直接栅极隧穿电流的氧化物层的电容器或被配置为电容器的晶体管，以及具有电压 容差高于电容/晶体管，其中电容器/晶体管通过经由开关施加跨越氧化物层的电压而被一次性地编程为反熔丝，以引起直接栅极隧穿电流从而将氧化物层破裂成 形成具有大约几百欧姆或更小的电阻的导电路径。

公开(公告)号：US06985387B2

公开(公告)日：2006-01-10

申请号：US10849295

申请日：2004-05-20

申请人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

发明人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

IPC分类号： G11C7/00 ,  H01L29/00

CPC分类号： G11C17/18 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write circuit, having first and second switches coupled to the capacitor, and a read circuit also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write circuit to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

摘要翻译： 一种能够以0.13μm或更低的CMOS技术制造的具有能够通过直接栅极隧穿电流的氧化物层的电容器或者被配置为电容器的晶体管的一次性编程存储元件。 还包括写入电路，其具有耦合到电容器的第一和第二开关，以及还耦合到电容器的读取电路。 电容器/晶体管通过经由写入电路施加跨越氧化物层的编程电压而被一次性地编程为反熔丝，以引起直接栅极隧穿电流破坏氧化物层，形成具有大约数百个电阻的电阻的导电路径 欧姆或更少。

公开(公告)号：US20050219889A1

公开(公告)日：2005-10-06

申请号：US11132335

申请日：2005-05-19

申请人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

发明人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

IPC分类号： G11C17/00 ,  G11C17/18 ,  H01L27/112

CPC分类号： G11C17/18 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

摘要翻译： 一种能够以0.13μm或更低的CMOS技术制造的具有能够通过直接栅极隧穿电流的氧化物层的电容器或者被配置为电容器的晶体管的一次性编程存储元件。 还包括具有耦合到电容器的第一和第二开关以及还耦合到电容器的读取开关的写开关。 电容器/晶体管通过经由写开关施加跨越氧化物层的编程电压作为反熔丝被一次性编程，以使直接栅极隧道电流破裂氧化层，形成具有大约数百个电阻的电阻的导电路径 欧姆或更少。

公开(公告)号：US07009891B2

公开(公告)日：2006-03-07

申请号：US11132335

申请日：2005-05-19

申请人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

发明人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

IPC分类号： H01L29/00 ,  G11C7/00

CPC分类号： G11C17/18 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

摘要翻译： 一种能够以0.13μm或更低的CMOS技术制造的具有能够通过直接栅极隧穿电流的氧化物层的电容器或者被配置为电容器的晶体管的一次性编程存储元件。 还包括具有耦合到电容器的第一和第二开关以及还耦合到电容器的读取开关的写开关。 电容器/晶体管通过经由写开关施加跨越氧化物层的编程电压作为反熔丝被一次性编程，以使直接栅极隧道电流破裂氧化层，形成具有大约数百个电阻的电阻的导电路径 欧姆或更少。

公开(公告)号：US06950355B2

公开(公告)日：2005-09-27

申请号：US10020208

申请日：2001-12-18

申请人： Surya Battacharya ,  Ming Chen ,  Guang-Jye Shiau ,  Liming Tsau ,  Henry Chen

发明人： Surya Battacharya ,  Ming Chen ,  Guang-Jye Shiau ,  Liming Tsau ,  Henry Chen

IPC分类号： G01R31/02 ,  G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C7/00

CPC分类号： G11C29/025 ,  G01R31/024 ,  G01R31/2853 ,  G01R31/2855 ,  G11C11/41 ,  G11C29/006 ,  G11C29/02

摘要： A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

摘要翻译： 一种用于测试半导体晶片的方法。 探针阵列耦合到半导体晶片。 然后在至少一个管芯的一个或多个SRAM阵列的多个相邻金属线对（例如，字线和/或位线对）之间施加电压差。 电压差的应用会引起金属桁条的故障或相邻线之间的缺陷。 此外，可以将电压施加在半导体晶片的多于一个裸片的一个或多个SRAM阵列的基本上所有平行金属线对的两对上。