公开(公告)号：US06950355B2

公开(公告)日：2005-09-27

申请号：US10020208

申请日：2001-12-18

申请人： Surya Battacharya ,  Ming Chen ,  Guang-Jye Shiau ,  Liming Tsau ,  Henry Chen

发明人： Surya Battacharya ,  Ming Chen ,  Guang-Jye Shiau ,  Liming Tsau ,  Henry Chen

IPC分类号： G01R31/02 ,  G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C7/00

CPC分类号： G11C29/025 ,  G01R31/024 ,  G01R31/2853 ,  G01R31/2855 ,  G11C11/41 ,  G11C29/006 ,  G11C29/02

摘要： A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.

摘要翻译： 一种用于测试半导体晶片的方法。 探针阵列耦合到半导体晶片。 然后在至少一个管芯的一个或多个SRAM阵列的多个相邻金属线对（例如，字线和/或位线对）之间施加电压差。 电压差的应用会引起金属桁条的故障或相邻线之间的缺陷。 此外，可以将电压施加在半导体晶片的多于一个裸片的一个或多个SRAM阵列的基本上所有平行金属线对的两对上。

公开(公告)号：US06985387B2

公开(公告)日：2006-01-10

申请号：US10849295

申请日：2004-05-20

申请人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

发明人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

IPC分类号： G11C7/00 ,  H01L29/00

CPC分类号： G11C17/18 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write circuit, having first and second switches coupled to the capacitor, and a read circuit also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write circuit to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

摘要翻译： 一种能够以0.13μm或更低的CMOS技术制造的具有能够通过直接栅极隧穿电流的氧化物层的电容器或者被配置为电容器的晶体管的一次性编程存储元件。 还包括写入电路，其具有耦合到电容器的第一和第二开关，以及还耦合到电容器的读取电路。 电容器/晶体管通过经由写入电路施加跨越氧化物层的编程电压而被一次性地编程为反熔丝，以引起直接栅极隧穿电流破坏氧化物层，形成具有大约数百个电阻的电阻的导电路径 欧姆或更少。

公开(公告)号：US20050219889A1

公开(公告)日：2005-10-06

申请号：US11132335

申请日：2005-05-19

申请人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

发明人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

IPC分类号： G11C17/00 ,  G11C17/18 ,  H01L27/112

CPC分类号： G11C17/18 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

摘要翻译： 一种能够以0.13μm或更低的CMOS技术制造的具有能够通过直接栅极隧穿电流的氧化物层的电容器或者被配置为电容器的晶体管的一次性编程存储元件。 还包括具有耦合到电容器的第一和第二开关以及还耦合到电容器的读取开关的写开关。 电容器/晶体管通过经由写开关施加跨越氧化物层的编程电压作为反熔丝被一次性编程，以使直接栅极隧道电流破裂氧化层，形成具有大约数百个电阻的电阻的导电路径 欧姆或更少。

公开(公告)号：US06960819B2

公开(公告)日：2005-11-01

申请号：US09739752

申请日：2000-12-20

申请人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

发明人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

IPC分类号： G11C17/00 ,  G11C17/18 ,  H01L27/112 ,  H01L29/00

CPC分类号： G11C17/18 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current, and a switch having a voltage tolerance higher than that of the capacitor/transistor, wherein the capacitor/transistor is one-time programmable as an anti-fuse by application of a voltage across the oxide layer via the switch to cause direct gate tunneling current to thereby rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

摘要翻译： 一种能够以0.13μm或更低的CMOS技术制造的一次性编程存储器元件，具有可以通过直接栅极隧穿电流的氧化物层的电容器或被配置为电容器的晶体管，以及具有电压 容差高于电容/晶体管，其中电容器/晶体管通过经由开关施加跨越氧化物层的电压而被一次性地编程为反熔丝，以引起直接栅极隧穿电流从而将氧化物层破裂成 形成具有大约几百欧姆或更小的电阻的导电路径。

公开(公告)号：US07009891B2

公开(公告)日：2006-03-07

申请号：US11132335

申请日：2005-05-19

申请人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

发明人： Vincent Chen ,  Henry Chen ,  Liming Tsau ,  Jay Shiau ,  Surya Battacharya ,  Akira Ito

IPC分类号： H01L29/00 ,  G11C7/00

CPC分类号： G11C17/18 ,  H01L27/112 ,  H01L2924/0002 ,  H01L2924/00

摘要： A one-time programming memory element, capable of being manufactured in a 0.13 μm or below CMOS technology, having a capacitor, or transistor configured as a capacitor, with an oxide layer capable of passing direct gate tunneling current. Also included is a write switch, having first and second switches coupled to the capacitor, and a read switch also coupled to the capacitor. The capacitor/transistor is one-time programmable as an anti-fuse by application of a program voltage across the oxide layer via the write switch to cause direct gate tunneling current to rupture the oxide layer to form a conductive path having resistance of approximately hundreds of ohms or less.

摘要翻译： 一种能够以0.13μm或更低的CMOS技术制造的具有能够通过直接栅极隧穿电流的氧化物层的电容器或者被配置为电容器的晶体管的一次性编程存储元件。 还包括具有耦合到电容器的第一和第二开关以及还耦合到电容器的读取开关的写开关。 电容器/晶体管通过经由写开关施加跨越氧化物层的编程电压作为反熔丝被一次性编程，以使直接栅极隧道电流破裂氧化层，形成具有大约数百个电阻的电阻的导电路径 欧姆或更少。

公开(公告)号：US20060145295A1

公开(公告)日：2006-07-06

申请号：US11365922

申请日：2006-03-02

申请人： Liming Tsau

发明人： Liming Tsau

IPC分类号： H01L29/00

CPC分类号： H01L28/60 ,  H01L21/76807 ,  Y10S438/957

摘要： A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.

摘要翻译： 金属绝缘体金属（MIM）电容器是根据铜双镶嵌工艺制成的。 如果形成在基底上的第一铜或铜合金金属层。 第一金属层的一部分用作MIM电容器的下板。 在后续层的蚀刻期间使用蚀刻停止介电层。 蚀刻停止层的一部分不被去除并且用作MIM电容器的绝缘体。 稍后在基板上形成第二铜或铜合金金属层。 第二金属层的一部分用作MIM电容器的上板。

公开(公告)号：US06833604B2

公开(公告)日：2004-12-21

申请号：US09971254

申请日：2001-10-03

申请人： Liming Tsau

发明人： Liming Tsau

IPC分类号： H01L2900

CPC分类号： H01L21/76807 ,  H01L23/5223 ,  H01L23/5252 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.

摘要翻译： 一种具有由双镶嵌制造工艺提供的第一导电层的电子结构; 由所述制造工艺提供的蚀刻停止层，并且与所述第一导电层电耦合，所述蚀刻停止层具有预选的介电常数和预定几何形状; 以及与所述蚀刻停止层电耦合的第二导电层。 该结构可以是例如金属 - 绝缘体 - 金属电容器，反熔丝等。

公开(公告)号：US20080042221A1

公开(公告)日：2008-02-21

申请号：US11505039

申请日：2006-08-15

申请人： Liming Tsau

发明人： Liming Tsau

IPC分类号： H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/4238

摘要： According to one exemplary embodiment, a transistor includes a channel region situated adjacent to a field oxide region. The transistor further includes a gate have a first portion situated over the channel region and a second portion situated over the field oxide region. The transistor further includes at least one gate contact situated on the second portion of the gate, where the second portion of the gate does not reduce a channel width of the channel region, and where the second portion of the gate does not increase gate resistance. According to this exemplary embodiment, the transistor further includes a drain active region, where the drain active region is surrounded by the gate. The transistor further includes a source active region surrounding the gate. The transistor further includes a well, where the channel region is situated between the well and the source active region.

摘要翻译： 根据一个示例性实施例，晶体管包括位于场氧化物区域附近的沟道区域。 晶体管还包括栅极，其具有位于沟道区域上方的第一部分和位于场氧化物区域上方的第二部分。 晶体管还包括位于栅极的第二部分上的至少一个栅极接触，其中栅极的第二部分不减小沟道区的沟道宽度，并且栅极的第二部分不增加栅极电阻。 根据该示例性实施例，晶体管还包括漏极有源区，其中漏极有源区被栅极包围。 晶体管还包括围绕栅极的源极有源区。 晶体管还包括阱，其中沟道区位于阱和源极活性区之间。

公开(公告)号：US08106476B2

公开(公告)日：2012-01-31

申请号：US11891902

申请日：2007-08-13

申请人： Robert I. Wu ,  Robert Lutze ,  Jung Kuan Wang ,  Voon Yean Ten ,  Liming Tsau

发明人： Robert I. Wu ,  Robert Lutze ,  Jung Kuan Wang ,  Voon Yean Ten ,  Liming Tsau

IPC分类号： H01L23/525

CPC分类号： H01L23/62 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.

摘要翻译： 根据一个示例性实施例，一种用于监测包括至少一个电监控结构的半导体晶片中的至少一个熔丝的结构完整性的方法包括在覆盖所述至少一个电监控结构的介电层中形成监测窗口，其中 在一个实施例中，在相同的蚀刻工艺中形成覆盖至少一个保险丝的保险丝窗口和保险丝窗口。 所述方法还包括在所述至少一个电监测结构上执行至少一个电测量，其中所述至少一个电测量用于监测所述至少一个熔丝的结构完整性。 利用至少一个电测量的变化来指示至少一个熔丝的结构完整性的变化。 至少一个电监控结构可以包括例如金属蛇纹线和一个或多个金属梳。

公开(公告)号：US07329955B2

公开(公告)日：2008-02-12

申请号：US11365922

申请日：2006-03-02

申请人： Liming Tsau

发明人： Liming Tsau

IPC分类号： H01L23/48

CPC分类号： H01L28/60 ,  H01L21/76807 ,  Y10S438/957

摘要： A metal-insulator-metal (MIM) capacitor is made according to a copper dual-damascene process. A first copper or copper alloy metal layer if formed on a substrate. A portion of the first metal layer is utilized as the lower plate of the MIM capacitor. An etch stop dielectric layer is used during etching of subsequent layers. A portion of an etch stop layer is not removed and is utilized as the insulator for the MIM capacitor. A second copper or copper alloy metal layer is later formed on the substrate. A portion of the second metal layer is utilized as the upper plate of the MIM capacitor.

摘要翻译： 金属绝缘体金属（MIM）电容器是根据铜双镶嵌工艺制成的。 如果形成在基底上的第一铜或铜合金金属层。 第一金属层的一部分用作MIM电容器的下板。 在后续层的蚀刻期间使用蚀刻停止介电层。 蚀刻停止层的一部分不被去除并且用作MIM电容器的绝缘体。 稍后在基板上形成第二铜或铜合金金属层。 第二金属层的一部分用作MIM电容器的上板。