公开(公告)号：US20120199898A1

公开(公告)日：2012-08-09

申请号：US13451009

申请日：2012-04-19

申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

IPC分类号： H01L27/115

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

公开(公告)号：US20120001252A1

公开(公告)日：2012-01-05

申请号：US12827947

申请日：2010-06-30

申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

IPC分类号： H01L27/115 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

公开(公告)号：US08330208B2

公开(公告)日：2012-12-11

申请号：US13451009

申请日：2012-04-19

申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

IPC分类号： H01L29/788

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

摘要翻译： 单片三维NAND串包括半导体通道，半导体通道的至少一个端部基本上垂直于基板的主表面延伸，多个控制栅电极具有基本上平行于基板的主表面延伸的带状 衬底，所述阻挡电介质包括多个阻挡电介质段，多个离散电荷存储段和位于所述多个离散电荷存储段和所述半导体通道中的每一个之间的隧道电介质。

公开(公告)号：US20110309430A1

公开(公告)日：2011-12-22

申请号：US13162550

申请日：2011-06-16

申请人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

发明人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

IPC分类号： H01L29/788 ,  H01L21/764

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649

摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

摘要翻译： 高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。 控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。 至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

公开(公告)号：US08946048B2

公开(公告)日：2015-02-03

申请号：US13162550

申请日：2011-06-16

申请人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

发明人： Vinod Robert Purayath ,  George Matamis ,  Henry Chien ,  James Kai ,  Yuan Zhang

IPC分类号： H01L21/76

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649

摘要： High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction.

摘要翻译： 高密度半导体存储器提供了非易失性存储器中分立器件之间的栅极耦合和电隔离的增强。 控制栅极和电荷存储区域之间的中间电介质在行方向上变化，不同的介电常数用于不同的材料以提供足够的栅极间耦合，同时防止边缘场和寄生电容。 至少部分地通过在列（位线）方向上形成的气隙和/或在行（字线）方向上形成的气隙来进一步提供电隔离。

公开(公告)号：US08187936B2

公开(公告)日：2012-05-29

申请号：US12827947

申请日：2010-06-30

申请人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

发明人： Johann Alsmeier ,  Vinod Robert Purayath ,  Henry Chien ,  George Matamis ,  Yao-Sheng Lee ,  James Kai ,  Yuan Zhang

IPC分类号： H01L21/336

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of making a monolithic three dimensional NAND string. The method includes forming a stack of alternating layers of a first material and a second material over a substrate. The first material includes a conductive or semiconductor control gate material and the second material includes an insulating material. The method also includes etching the stack to form at least one opening in the stack, selectively etching the first material to form first recesses in the first material and forming a blocking dielectric in the first recesses. The method also includes forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric, forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening and forming a semiconductor channel in the at least one opening.

摘要翻译： 制造单片三维NAND串的方法。 该方法包括在衬底上形成第一材料和第二材料的交替层的叠层。 第一材料包括导电或半导体控制栅极材料，第二材料包括绝缘材料。 该方法还包括蚀刻堆叠以在堆叠中形成至少一个开口，选择性地蚀刻第一材料以在第一材料中形成第一凹槽并在第一凹槽中形成阻挡电介质。 该方法还包括在隔离电介质上的第一凹槽中形成彼此分开的多个离散的电荷存储段，在暴露在至少一个开口中的离散电荷存储段的侧壁上形成隧道电介质，并形成半导体 通道在至少一个开口中。

公开(公告)号：US20110309426A1

公开(公告)日：2011-12-22

申请号：US13163538

申请日：2011-06-17

申请人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/764

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

摘要翻译： 提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。 在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。 侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。 至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

公开(公告)号：US08492224B2

公开(公告)日：2013-07-23

申请号：US13163538

申请日：2011-06-17

申请人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

发明人： Vinod Robert Purayath ,  Tuan Pham ,  Hiroyuki Kinoshita ,  Yuan Zhang ,  Henry Chin ,  James K. Kai ,  Takashi W. Orimoto ,  George Matamis ,  Henry Chien

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/764

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

摘要翻译： 提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。 在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。 侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。 至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

公开(公告)号：US08946803B2

公开(公告)日：2015-02-03

申请号：US11951998

申请日：2007-12-06

申请人： George Matamis ,  Henry Chien ,  Vinod Robert Purayath ,  Takashi Whitney Orimoto ,  James Kai

发明人： George Matamis ,  Henry Chien ,  Vinod Robert Purayath ,  Takashi Whitney Orimoto ,  James Kai

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L27/115 ,  H01L27/108 ,  H01L29/423

CPC分类号： H01L21/28273 ,  H01L27/10844 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.

摘要翻译： 浮动栅极存储器阵列的浮动栅极在位线方向和字线方向都具有倒T形。 使用分离形成浮动栅极的两个多晶硅层的蚀刻停止层形成浮动栅极。 字线在一个示例中在浮动栅极上延伸，并且在另一示例中，字线在浮动栅极之间延伸。

公开(公告)号：US20090147576A1

公开(公告)日：2009-06-11

申请号：US11951998

申请日：2007-12-06

申请人： George Matamis ,  Henry Chien ,  Vinod Robert Purayath ,  Takashi Whitney Orimoto ,  James Kai

发明人： George Matamis ,  Henry Chien ,  Vinod Robert Purayath ,  Takashi Whitney Orimoto ,  James Kai

IPC分类号： G11C16/04 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/10844 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： Floating gates of a floating gate memory array have an inverted-T shape in both the bit line direction and the word line direction. Floating gates are formed using an etch stop layer that separates two polysilicon layers that form floating gates. Word lines extend over floating gates in one example, and word lines extend between floating gates in another example.

摘要翻译： 浮动栅极存储器阵列的浮动栅极在位线方向和字线方向都具有倒T形。 使用分离形成浮动栅极的两个多晶硅层的蚀刻停止层形成浮动栅极。 字线在一个示例中在浮动栅极上延伸，并且在另一示例中，字线在浮动栅极之间延伸。