Semiconductor Processing Methods, And Methods Of Forming Isolation Structures
    1.
    发明申请
    Semiconductor Processing Methods, And Methods Of Forming Isolation Structures 有权
    半导体加工方法和形成隔离结构的方法

    公开(公告)号:US20120329231A1

    公开(公告)日:2012-12-27

    申请号:US13603100

    申请日:2012-09-04

    IPC分类号: H01L21/762 H01L21/336

    摘要: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    摘要翻译: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料(例如,聚硅氮烷)可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后,可以将一种或多种掺杂剂物质注入到投影中,使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构,其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域,其中上部区域为至少75%的无定形,并且下部区域是完全结晶的。

    Semiconductor processing methods, and methods of forming isolation structures
    2.
    发明授权
    Semiconductor processing methods, and methods of forming isolation structures 有权
    半导体加工方法和形成隔离结构的方法

    公开(公告)号:US08906771B2

    公开(公告)日:2014-12-09

    申请号:US13603100

    申请日:2012-09-04

    摘要: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    摘要翻译: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料(例如,聚硅氮烷)可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后,可以将一种或多种掺杂剂物质注入到投影中,使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构,其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域,其中上部区域为至少75%的无定形,并且下部区域是完全结晶的。

    Semiconductor constructions
    3.
    发明授权
    Semiconductor constructions 失效
    半导体结构

    公开(公告)号:US08274081B2

    公开(公告)日:2012-09-25

    申请号:US12728942

    申请日:2010-03-22

    IPC分类号: H01L29/04 H01L33/16

    摘要: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    摘要翻译: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料(例如,聚硅氮烷)可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后,可以将一种或多种掺杂剂物质注入到投影中,使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构,其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域,其中上部区域为至少75%的无定形,并且下部区域是完全结晶的。

    Semiconductor Constructions, Semiconductor Processing Methods, And Methods Of Forming Isolation Structures
    4.
    发明申请
    Semiconductor Constructions, Semiconductor Processing Methods, And Methods Of Forming Isolation Structures 失效
    半导体结构,半导体加工方法和形成隔离结构的方法

    公开(公告)号:US20110227071A1

    公开(公告)日:2011-09-22

    申请号:US12728942

    申请日:2010-03-22

    摘要: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

    摘要翻译: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料(例如,聚硅氮烷)可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后,可以将一种或多种掺杂剂物质注入到投影中,使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构,其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域,其中上部区域为至少75%的无定形,并且下部区域是完全结晶的。

    Methods of forming semiconductor devices having diffusion regions of reduced width
    5.
    发明授权
    Methods of forming semiconductor devices having diffusion regions of reduced width 有权
    形成具有减小宽度的扩散区域的半导体器件的方法

    公开(公告)号:US08709929B2

    公开(公告)日:2014-04-29

    申请号:US13604411

    申请日:2012-09-05

    IPC分类号: H01L21/265 H01L29/78

    摘要: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion regions in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.

    摘要翻译: 提供了用于形成半导体器件的半导体器件和方法,包括在半导体中包括一个或多个扩散区域的半导体器件,所述一个或多个扩散区域与邻近半导体表面形成的栅极相邻(例如,半导体衬底 )。 一个或多个扩散区域包括在半导体表面下方的深度处的第一宽度和靠近半导体表面的第二宽度,一个或多个扩散区域的第二宽度小于第一宽度的大约40% 宽度。

    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH
    6.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH 有权
    形成具有减小宽度扩散区域的半导体器件的方法

    公开(公告)号:US20120329258A1

    公开(公告)日:2012-12-27

    申请号:US13604411

    申请日:2012-09-05

    IPC分类号: H01L21/265

    摘要: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.

    摘要翻译: 提供了用于形成半导体器件的半导体器件和方法,包括在半导体中包括一个或多个扩散区的半导体器件,所述一个或多个扩散区与邻近半导体表面形成的栅极(例如,半导体衬底 )。 一个或多个扩散区域包括在半导体表面下方的深度处的第一宽度和靠近半导体表面的第二宽度,一个或多个扩散区域的第二宽度小于第一宽度的大约40% 宽度。

    Semiconductor devices and methods of forming semiconductor devices having diffusion regions of reduced width
    7.
    发明授权
    Semiconductor devices and methods of forming semiconductor devices having diffusion regions of reduced width 有权
    形成半导体器件的半导体器件和方法,该半导体器件具有减小宽度的扩散区域

    公开(公告)号:US08283708B2

    公开(公告)日:2012-10-09

    申请号:US12562635

    申请日:2009-09-18

    IPC分类号: H01L29/78 H01L21/336

    摘要: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of the one or more diffusion regions being less than about 40% greater than the first width.

    摘要翻译: 提供了用于形成半导体器件的半导体器件和方法,包括在半导体中包括一个或多个扩散区的半导体器件,所述一个或多个扩散区与邻近半导体表面形成的栅极(例如,半导体衬底 )。 一个或多个扩散区域包括在半导体表面下方的深度处的第一宽度和靠近半导体表面的第二宽度,一个或多个扩散区域的第二宽度小于第一宽度的大约40% 宽度。

    SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH
    8.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING DIFFUSION REGIONS OF REDUCED WIDTH 有权
    半导体器件和形成具有减小宽度扩散区域的半导体器件的方法

    公开(公告)号:US20110068378A1

    公开(公告)日:2011-03-24

    申请号:US12562635

    申请日:2009-09-18

    IPC分类号: H01L29/78 H01L21/336

    摘要: Semiconductor devices and methods for forming semiconductor devices are provided, including semiconductor devices that comprise one or more diffusion region in a semiconductor, the one or more diffusion regions being adjacent to a gate formed adjacent to a surface of the semiconductor (e.g., a semiconductor substrate). The one or more diffusion regions comprise a first width at a depth below the surface of the semiconductor and a second width near the surface of the semiconductor, the second width of at the one or more diffusion regions being less than about 40% greater than the first width.

    摘要翻译: 提供了用于形成半导体器件的半导体器件和方法,包括在半导体中包括一个或多个扩散区的半导体器件,所述一个或多个扩散区与邻近半导体表面形成的栅极(例如,半导体衬底 )。 一个或多个扩散区域包括在半导体表面下方的深度处的第一宽度和靠近半导体表面的第二宽度,在一个或多个扩散区域处的第二宽度小于大约40% 第一宽

    Charger box
    9.
    外观设计

    公开(公告)号:USD972505S1

    公开(公告)日:2022-12-13

    申请号:US29842827

    申请日:2022-06-16

    申请人: Lequn Liu

    设计人: Lequn Liu

    Eye wear visually enhancing laser spot and laser line

    公开(公告)号:US11454751B2

    公开(公告)日:2022-09-27

    申请号:US16501587

    申请日:2019-05-04

    摘要: An eye wear comprises an optical filter disposed in front of an eye. The optical filter has a transmittance function of wavelength comprising a transmittance peak having a peak transmittance and a transmittance bandwidth. A transmittance outside the transmittance peak is at a lower level transmittance, wherein a ratio of the lower level transmittance to the peak transmittance is less than unity. The transmittance peak is at a central wavelength of a laser that emits laser light forming one of a laser spot and a laser line. The transmittance bandwidth is larger than a bandwidth of the laser light emitted by the laser. The laser spot or the laser line formed by the laser light emitted by the laser is viewed through the eye wear.