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公开(公告)号：US08853833B2
公开(公告)日：2014-10-07
申请号：US13159203
申请日：2011-06-13
IPC分类号： H01L23/552 , H01L23/522
CPC分类号： H01L23/552 , H01L23/5225 , H01L23/5226 , H01L23/53271 , H01L27/088 , H01L29/402 , H01L29/404 , H01L29/45 , H01L29/7833 , H01L2924/0002 , H03K17/161 , H03K17/162 , H01L2924/00
摘要： Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.
摘要翻译： 描述半导体器件以及包括它们的方法和系统。 一种这样的器件包括在半导体材料中的扩散区域，耦合到扩散区域的端子和耦合到端子并且从端子在扩散区域上延伸以屏蔽扩散区域的场板。 还描述了另外的实施例。
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公开(公告)号：US20120313691A1
公开(公告)日：2012-12-13
申请号：US13159203
申请日：2011-06-13
IPC分类号： H03K3/01 , H01L27/04 , H01L23/552
CPC分类号： H01L23/552 , H01L23/5225 , H01L23/5226 , H01L23/53271 , H01L27/088 , H01L29/402 , H01L29/404 , H01L29/45 , H01L29/7833 , H01L2924/0002 , H03K17/161 , H03K17/162 , H01L2924/00
摘要： Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.
摘要翻译： 描述半导体器件以及包括它们的方法和系统。 一种这样的器件包括在半导体材料中的扩散区域，耦合到扩散区域的端子和耦合到端子并且从端子在扩散区域上延伸以屏蔽扩散区域的场板。 还描述了另外的实施例。
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3.发明申请Method and circuit for adjusting the timing of output data based on an operational mode of output drivers 失效基于输出驱动器的操作模式来调整输出数据的时序的方法和电路公开(公告)号：US20050035799A1
公开(公告)日：2005-02-17
申请号：US10944136
申请日：2004-09-16
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , H03L7/0812
摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
摘要翻译： 延迟锁定环路调整响应于外部时钟信号而产生的时钟信号的延迟。 时钟信号被施加到输出缓冲器以对缓冲器进行时钟，使得来自缓冲器的数据或时钟信号与外部时钟信号同步。 响应于分别具有第一和第二逻辑状态的输出驱动强度位，输出缓冲器以全驱动和降低驱动模式工作。 延迟锁定环路响应于输出驱动强度位的状态来调整时钟信号的延迟，以在两种操作模式期间保持来自缓冲器的数据或时钟信号同步。
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4.发明授权Method and circuit for adjusting the timing of output data based on an operational mode of output drivers 失效基于输出驱动器的操作模式来调整输出数据的时序的方法和电路公开(公告)号：US06693472B2
公开(公告)日：2004-02-17
申请号：US10243279
申请日：2002-09-12
IPC分类号： H03L706
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , H03L7/0812
摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
摘要翻译： 延迟锁定环路调整响应于外部时钟信号而产生的时钟信号的延迟。 时钟信号被施加到输出缓冲器以对缓冲器进行时钟，使得来自缓冲器的数据或时钟信号与外部时钟信号同步。 响应于分别具有第一和第二逻辑状态的输出驱动强度位，输出缓冲器以全驱动和降低驱动模式工作。 延迟锁定环路响应于输出驱动强度位的状态来调整时钟信号的延迟，以在两种操作模式期间保持来自缓冲器的数据或时钟信号同步。
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5.发明申请公开(公告)号：US20120329231A1
公开(公告)日：2012-12-27
申请号：US13603100
申请日：2012-09-04
申请人： Vladimir Mikhalev , Jim Fulford , Yongjun Jeff Hu , Gordon A. Haller , Lequn Liu
发明人： Vladimir Mikhalev , Jim Fulford , Yongjun Jeff Hu , Gordon A. Haller , Lequn Liu
IPC分类号： H01L21/762 , H01L21/336
CPC分类号： H01L21/823462 , H01L21/02107 , H01L21/02164 , H01L21/02282 , H01L21/265 , H01L21/76224 , H01L21/76832 , H01L21/76834 , H01L21/823425 , H01L21/823481 , H01L29/66575 , H01L29/78 , H01L29/7846
摘要： Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
摘要翻译： 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。
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公开(公告)号：US08243526B2
公开(公告)日：2012-08-14
申请号：US12653437
申请日：2009-12-14
申请人： Michael Smith , Vladimir Mikhalev , Kenneth Marr , Haitao Liu
发明人： Michael Smith , Vladimir Mikhalev , Kenneth Marr , Haitao Liu
CPC分类号： H01L27/11526 , H01L27/0266 , H01L27/11529
摘要： A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines.
摘要翻译： 一种非易失性微电子存储器件，其包括耗尽模式电路保护装置，其防止在擦除操作期间施加到位线的高电压被施加到和电连接到位线的低电压电路。
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7.发明授权Method and apparatus for improving output skew for synchronous integrated circuits 失效改善同步集成电路输出偏移的方法和装置公开(公告)号：US07272742B2
公开(公告)日：2007-09-18
申请号：US10931358
申请日：2004-08-31
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F1/12 , G06F13/4217
摘要： A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffered clock signal and generates a delayed clock signal, and an output circuit including output signal paths for outputting the output signals synchronously with the system clock signal by using the delayed clock signal. At least one of the output signal paths includes a delay circuit and an output buffer. Each delay circuit provides a programmable delay to the delayed clock signal to generate a unique delayed clock signal used to clock an output signal into the respective output buffer. By programming the delays based upon output skew, the output skew can be improved.
摘要翻译： 一种用于改善跨同步集成电路器件的数据总线的输出偏移的方法和装置。 该装置包括时钟输入缓冲器，其接收系统时钟信号并产生缓冲的时钟信号，延迟线，其接收经缓冲的时钟信号并产生延迟的时钟信号;以及输出电路，包括用于同步输出输出信号的输出信号路径 通过使用延迟的时钟信号与系统时钟信号。 输出信号路径中的至少一个包括延迟电路和输出缓冲器。 每个延迟电路为延迟的时钟信号提供可编程延迟，以产生用于将输出信号时钟输入到相应输出缓冲器中的唯一的延迟时钟信号。 通过基于输出偏移来编程延迟，可以提高输出偏移。
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公开(公告)号：US06975149B2
公开(公告)日：2005-12-13
申请号：US10944136
申请日：2004-09-16
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1066 , H03L7/0812
摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.
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公开(公告)号：US20050034006A1
公开(公告)日：2005-02-10
申请号：US10931358
申请日：2004-08-31
CPC分类号： G06F1/10 , G06F1/12 , G06F13/4217
摘要： A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffered clock signal and generates a delayed clock signal, and an output circuit including output signal paths for outputting the output signals synchronously with the system clock signal by using the delayed clock signal. At least one of the output signal paths includes a delay circuit and an output buffer. Each delay circuit provides a programmable delay to the delayed clock signal to generate a unique delayed clock signal used to clock an output signal into the respective output buffer. By programming the delays based upon output skew, the output skew can be improved.
摘要翻译： 一种用于改善跨同步集成电路器件的数据总线的输出偏移的方法和装置。 该装置包括时钟输入缓冲器，其接收系统时钟信号并产生缓冲的时钟信号，延迟线，其接收经缓冲的时钟信号并产生延迟的时钟信号;以及输出电路，包括用于同步输出输出信号的输出信号路径 通过使用延迟的时钟信号与系统时钟信号。 输出信号路径中的至少一个包括延迟电路和输出缓冲器。 每个延迟电路为延迟的时钟信号提供可编程延迟，以产生用于将输出信号时钟输入到相应输出缓冲器中的唯一的延迟时钟信号。 通过基于输出偏移来编程延迟，可以提高输出偏移。
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公开(公告)号：USRE46005E1
公开(公告)日：2016-05-17
申请号：US11800520
申请日：2007-05-04
申请人： Vladimir Mikhalev , Feng Lin
发明人： Vladimir Mikhalev , Feng Lin
CPC分类号： H03L7/0814 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/135 , H03L7/00 , H03L7/0812
摘要： A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal and a control circuit configured to control the main delay line to vary the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal responsive to assertion of an enable signal. The detection circuit is configured to receive the input clock signal and the feedback clock signal, detect a phase alignment error between the input clock signal and the feedback clock signal, and assert the enable signal responsive to the phase alignment error exceeding a predetermined amount. A method for synchronizing clock signals includes receiving an input clock signal; delaying the input clock signal by a time interval to generate an output clock signal; controlling the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal responsive to assertion of an enable signal; detecting a phase alignment error between the input clock signal and the feedback clock signal; and asserting the enable signal responsive to the phase alignment error exceeding a predetermined amount.
摘要翻译： 定时控制电路包括同步电路和检测电路。 同步电路包括：主延迟线，被配置为接收输入时钟信号并延迟输入时钟信号一段时间间隔以产生输出时钟信号;以及控制电路，被配置为控制主延迟线以改变时间间隔以同步 输入时钟信号与响应于使能信号的断言从输出时钟信号产生的反馈时钟信号。 检测电路被配置为接收输入时钟信号和反馈时钟信号，检测输入时钟信号和反馈时钟信号之间的相位对准误差，并响应超过预定量的相位对准误差来确定使能信号。 一种用于同步时钟信号的方法包括接收输入时钟信号; 将输入时钟信号延迟时间间隔以产生输出时钟信号; 响应于使能信号的断言，控制所述时间间隔以使所述输入时钟信号与从所述输出时钟信号产生的反馈时钟信号同步; 检测输入时钟信号和反馈时钟信号之间的相位对准误差; 并且响应于超过预定量的相位对准误差来确定使能信号。
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