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13 条记录 (耗时 0.019 秒)

    Termination resistance independent system for impedance matching in high speed input-output chip interfacing
    1.
    发明授权
    Termination resistance independent system for impedance matching in high speed input-output chip interfacing 有权

    公开(公告)号：US06278339B1

    公开(公告)日：2001-08-21

    申请号：US09735679

    申请日：2000-12-13

    申请人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

    发明人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

    IPC分类号： H03H738

    摘要： An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit. Optionally, the impedance matching network further comprises a control circuit which detects overshoots and undershoots on the driver circuit output and provides a control current proportional to the magnitude of overshoots and undershoots to an electromagnetic adjustment mechanism which provides a linear adjustment to the moveable stub proportional to the control current.

    Termination impedance independent system for impedance matching in high speed input-output chip interfacing
    2.
    发明授权
    Termination impedance independent system for impedance matching in high speed input-output chip interfacing 有权
    用于高速输入 - 输出芯片接口中阻抗匹配的终端电阻独立系统

    公开(公告)号：US06249193B1

    公开(公告)日：2001-06-19

    申请号：US09320902

    申请日：1999-05-27

    申请人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

    发明人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

    IPC分类号： H03H738

    CPC分类号： H04L25/0278

    摘要： An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit. Optionally, the impedance matching network further comprises a control circuit which detects overshoots and undershoots on the driver circuit output and provides a control current proportional to the magnitude of overshoots and undershoots to an electromagnetic adjustment mechanism which provides a linear adjustment to the moveable stub proportional to the control current.

    摘要翻译： 阻抗匹配系统和用于高频输入 - 输出设备的驱动电路输出端的阻抗匹配网络。 阻抗匹配网络包括可调节长度的传输线，其长度与驱动器电路输出上的瞬变的大小成比例地调整，并且输入阻抗是纯反应的，并且是其长度的函数。 可调长度传输线的目的是通过为驱动器电路的接收器电路的阻抗的无功分量提供匹配阻抗来降低瞬态电压。 在优选实施例中，阻抗匹配网络包括形成在系统卡上的两条平行导线，由可移动短截线短路，并且与驱动电路并联连接。 可选地，阻抗匹配网络还包括控制电路，其检测驱动器电路输出端的过冲和下冲，并提供与过冲和下冲的大小成比例的控制电流到电磁调节机构，该电磁调节机构对可移动短截线进行线性调节，与 控制电流。

    On-chip automatic system for impedance matching in very high speed input-output chip interfacing
    3.
    发明授权
    On-chip automatic system for impedance matching in very high speed input-output chip interfacing 有权
    用于在非常高速的输入输出芯片接口中进行阻抗匹配的片上自动系统

    公开(公告)号：US6140885A

    公开(公告)日：2000-10-31

    申请号：US255997

    申请日：1999-02-23

    申请人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

    发明人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

    IPC分类号： H04L25/02 ,  H03H7/38 ,  H03H7/40

    CPC分类号： H04L25/0278

    摘要： An impedance matching system and a network for automatic impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises a control circuit which varies a control voltage proportionally to the frequency of voltage transients that occur on the driver circuit output, an adjustment mechanism which provides a linear motion proportional to the control voltage, and an adjustable length transmission line whose length is adjusted in proportion to the frequency of voltage transients on the driver circuit output and whose impedance, which is purely reactive, is proportional to its length. The purpose of the adjustable length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver network to the driver circuit. In the preferred embodiment, the impedance matching network is manufactured on the same chip as the driver circuit.

    摘要翻译： 阻抗匹配系统和用于高频输入输出设备的驱动电路输出端的自动阻抗匹配网络。 阻抗匹配网络包括控制电路，该控制电路根据驱动器电路输出上发生的电压瞬变的频率成比例地改变控制电压，提供与控制电压成比例的线性运动的调节机构，以及可调长度传输线，其长度 与驱动器电路输出上的电压瞬变的频率成比例地调整，并且其纯粹无功的阻抗与其长度成比例。 可调长度传输线的目的是通过为接收机网络的阻抗的无功分量提供与驱动器电路的匹配阻抗来减小瞬态电压。 在优选实施例中，阻抗匹配网络在与驱动器电路相同的芯片上制造。

    Area efficient, sequential gray code to thermometer code decoder
    4.
    发明授权
    Area efficient, sequential gray code to thermometer code decoder 有权

    公开(公告)号：US06617986B2

    公开(公告)日：2003-09-09

    申请号：US09682449

    申请日：2001-09-04

    申请人： John Connor ,  Patrick R. Hansen ,  Steven Leschuk ,  Jason E. Rotella

    发明人： John Connor ,  Patrick R. Hansen ,  Steven Leschuk ,  Jason E. Rotella

    IPC分类号： H03M704

    CPC分类号： H03M7/16 ,  H03M7/165

    摘要： A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

    Structure and method of alternating precharge in dynamic SOI circuits
    8.
    发明授权
    Structure and method of alternating precharge in dynamic SOI circuits 失效
    动态SOI电路中交替预充电的结构和方法

    公开(公告)号：US06441646B1

    公开(公告)日：2002-08-27

    申请号：US09682903

    申请日：2001-10-31

    申请人： George M. Braceras ,  Patrick R. Hansen

    发明人： George M. Braceras ,  Patrick R. Hansen

    IPC分类号： H03K19091

    CPC分类号： H03K19/0963

    摘要： A structure and method for reducing bipolar current in of a SOI circuit by alternating precharge low and precharge high methodologies comprises a reset signal source coupled to an inverter and a primary node, further coupled to a first and second PFET device; a clock signal source; coupled to a first NFET device and a third PFET device; a first input signal source coupled to a second NFET device and a fourth PFET device; a first NFET stack node coupled to the third PFET device, the first NFET device, the primary node, and the second NFET device; a second input signal source coupled to a third NFET device; a fifth PFET device coupled to the fourth PFET device; a power supply voltage source coupled to the fifth PFET device; and a second NFET node coupled to the fourth PFET device, the second NFET device, and the third NFET device.

    摘要翻译： 通过交替预充电低和预充电高方法来减少SOI电路中的双极电流的结构和方法包括耦合到反相器和主节点的复位信号源，还耦合到第一和第二PFET器件; 时钟信号源; 耦合到第一NFET器件和第三PFET器件; 耦合到第二NFET器件和第四PFET器件的第一输入信号源; 耦合到第三PFET器件，第一NFET器件，主节点和第二NFET器件的第一NFET堆叠节点; 耦合到第三NFET器件的第二输入信号源; 耦合到第四PFET器件的第五PFET器件; 耦合到所述第五PFET器件的电源电压源; 以及耦合到第四PFET器件，第二NFET器件和第三NFET器件的第二NFET节点。