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公开(公告)号：US08243488B2
公开(公告)日：2012-08-14
申请号：US13270587
申请日：2011-10-11
Applicant: Shiro Harashima , Wataru Tsukada
Inventor： Shiro Harashima , Wataru Tsukada
IPC: G11C5/02
Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。
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公开(公告)号：US20120026772A1
公开(公告)日：2012-02-02
申请号：US13270587
申请日：2011-10-11
Applicant: Shiro Harashima , Wataru Tsukada
Inventor： Shiro Harashima , Wataru Tsukada
IPC: G11C5/02
Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。
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公开(公告)号：US20120281348A1
公开(公告)日：2012-11-08
申请号：US13549949
申请日：2012-07-16
Applicant: Shiro Harashima , Wataru Tsukada
Inventor： Shiro Harashima , Wataru Tsukada
IPC: H05K7/06
Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
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公开(公告)号：US08054664B2
公开(公告)日：2011-11-08
申请号：US12638382
申请日：2009-12-15
Applicant: Shiro Harashima , Wataru Tsukada
Inventor： Shiro Harashima , Wataru Tsukada
IPC: G11C5/02
Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。
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Patent Agency Ranking
公开(公告)号：US08054643B2
公开(公告)日：2011-11-08
申请号：US12320641
申请日：2009-01-30
Applicant: Wataru Tsukada
Inventor： Wataru Tsukada
IPC: H05K7/02
CPC classification number: H05K1/181 , H05K2201/09245 , H05K2201/097 , H05K2201/10159 , H05K2201/10689 , Y02P70/611 , Y10T29/4913
Abstract: A semiconductor module includes a plurality of rectangular shaped semiconductor devices which are arranged in two rows such that each pair of adjacent semiconductor devices is in orientations differed by 90 degrees from each other. A plurality of wirings connect the semiconductor devices included in one of the two rows to the semiconductor devices included in the other row such that the semiconductor devices arranged in the same orientations are connected to each other.
Abstract translation: 半导体模块包括多个矩形半导体器件，它们被布置成两行，使得每对相邻的半导体器件的取向彼此相差90度。 多个布线将包括在两行之一中的半导体器件连接到另一行中包括的半导体器件，使得以相同取向排列的半导体器件彼此连接。
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公开(公告)号：US20100157645A1
公开(公告)日：2010-06-24
申请号：US12638382
申请日：2009-12-15
Applicant: Shiro Harashima , Wataru Tsukada
Inventor： Shiro Harashima , Wataru Tsukada
Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。
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7.发明授权公开(公告)号：US08510629B2
公开(公告)日：2013-08-13
申请号：US12908512
申请日：2010-10-20
Applicant: Wataru Tsukada , Shiro Harashima , Yoji Nishio
Inventor： Wataru Tsukada , Shiro Harashima , Yoji Nishio
IPC: G11C29/00
CPC classification number: G06F11/1044 , H03M13/13
Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.
Abstract translation: 将其中存储用户数据的常规芯片封装和存储其中的纠错码的纠错芯片封装安装在模块基板上。 模块基板在X方向上具有不同坐标的第一和第二安装区域，并且第二安装区域具有不同Y坐标的第三和第四安装区域。 常规包装件相对地布置在模块基板的表面和背面上的第一安装区域中。 纠错芯片封装相对地布置在模块基板的表面和背面上的第三安装区域中。 缓冲用户数据和纠错码的存储器缓冲器布置在第四安装区域中。
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公开(公告)号：US08462535B2
公开(公告)日：2013-06-11
申请号：US13549949
申请日：2012-07-16
Applicant: Shiro Harashima , Wataru Tsukada
Inventor： Shiro Harashima , Wataru Tsukada
IPC: G11C5/02
Abstract: The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
Abstract translation: 本发明提供了符合LR-DIMM技术的VLP型LR-DIMM的新型接线方法。 LR-DIMM包括安装在板上的多个DRAM，安装在板上用于接收数据的两个连接器和安装在板上的缓冲器装置，用于重新应用于两个连接器的数据以将数据提供给多个DRAM。 缓冲装置位于两个连接器两端布置的板的中心附近，并且将来自每个连接器的数据提供给布置在与连接器相对的DRAM上的数据。
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公开(公告)号：US20090236758A1
公开(公告)日：2009-09-24
申请号：US12408981
申请日：2009-03-23
Applicant: Wataru Tsukada
Inventor： Wataru Tsukada
IPC: H01L23/538
CPC classification number: H05K1/181 , G11C5/063 , H01L23/5386 , H01L25/0655 , H01L2924/0002 , H01L2924/3011 , H05K2201/09227 , H05K2201/10689 , Y02P70/611 , H01L2924/00
Abstract: A semiconductor module has a plurality of semiconductor devices arranged on a substrate and mutually connected by signal bus wiring lines. Each pair of first semiconductor devices are connected to each other by the signal bus wiring lines, skipping a second semiconductor device located between the pair of first semiconductor devices.
Abstract translation: 半导体模块具有布置在基板上并由信号总线布线相互连接的多个半导体器件。 每对第一半导体器件通过信号总线布线彼此连接，跳过位于该对第一半导体器件之间的第二半导体器件。
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