公开(公告)号：US20060168497A1

公开(公告)日：2006-07-27

申请号：US11040140

申请日：2005-01-21

申请人： Wei-Yi Xiao ,  Dean Blair ,  Thomas Ruane ,  William Lewis

发明人： Wei-Yi Xiao ,  Dean Blair ,  Thomas Ruane ,  William Lewis

IPC分类号： H03M13/00

CPC分类号： G06F17/5022

摘要： A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

摘要翻译： 基于微处理器底层硬件设计的微处理器仿真方法，系统和程序产品。 该方法，系统和程序产品停止模拟测试用例的正常功能，启动扫描时钟，在初始时刻记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。 比较“快照”，如果“快照”都相同，则功能扫描成功。 但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

公开(公告)号：US07559002B2

公开(公告)日：2009-07-07

申请号：US11754941

申请日：2007-05-29

申请人： Wei-Yi Xiao ,  Dean Gilbert Bair ,  Thomas Ruane ,  William Lewis

发明人： Wei-Yi Xiao ,  Dean Gilbert Bair ,  Thomas Ruane ,  William Lewis

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F17/5022

摘要： A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

摘要翻译： 基于微处理器底层硬件设计的微处理器仿真方法，系统和程序产品可以停止模拟测试用例的正常功能，启动扫描时钟，并将扫描环数据的第一个“快照”记录在 最初的时间。 然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。 比较“快照”，如果“快照”都相同，则功能扫描成功。 但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

公开(公告)号：US07509552B2

公开(公告)日：2009-03-24

申请号：US11040140

申请日：2005-01-21

申请人： Wei-Yi Xiao ,  Dean G. Blair ,  Thomas Ruane ,  William Lewis

发明人： Wei-Yi Xiao ,  Dean G. Blair ,  Thomas Ruane ,  William Lewis

IPC分类号： G01R31/28 ,  G06F7/02

CPC分类号： G06F17/5022

摘要： A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

摘要翻译： 基于微处理器底层硬件设计的微处理器仿真方法，可以在初始时间停止模拟测试仪的正常功能，启动扫描时钟，并记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。 比较“快照”，如果“快照”都相同，则功能扫描成功。 但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

公开(公告)号：US20070255997A1

公开(公告)日：2007-11-01

申请号：US11754941

申请日：2007-05-29

申请人： Wei-Yi Xiao ,  Dean Bair ,  Thomas Ruane ,  William Lewis

发明人： Wei-Yi Xiao ,  Dean Bair ,  Thomas Ruane ,  William Lewis

IPC分类号： H03M13/00

CPC分类号： G06F17/5022

摘要： A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

摘要翻译： 基于微处理器底层硬件设计的微处理器仿真方法，系统和程序产品。 该方法，系统和程序产品停止模拟测试用例的正常功能，启动扫描时钟，在初始时刻记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转（移动）扫描环，并且当扫描时钟停止时（扫描时钟的停止基于扫描环上的锁存器的数量被控制），另一个“快照” 的扫描环数据。 比较“快照”，如果“快照”都相同，则功能扫描成功。 但是，如果功能扫描验证无法正确旋转扫描链，也就是说，如果两个“快照”中的一些闩锁不匹配，则有必要将断点定位在大量扫描锁存器内。

公开(公告)号：US20050251379A1

公开(公告)日：2005-11-10

申请号：US10835324

申请日：2004-04-29

申请人： William Lewis ,  Wei-Yi Xiao

发明人： William Lewis ,  Wei-Yi Xiao

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/40 ,  G06F11/26 ,  G06F17/50

CPC分类号： G06F17/5022

摘要： A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.

摘要翻译： 一种在模拟环境中的寄存器管理方法，包括从指令单元解码流水线接收指令。 如果指令是AGI指令，则在仿真环境中执行地址生成互锁（AGI）功能。 执行AGI功能响应于由寄存器管理器和指令控制的寄存器池。 如果指令是早期AGI指令，则在仿真环境中执行早期AGI功能。 执行早期AGI功能可以响应寄存器池和指令。

公开(公告)号：US08484007B2

公开(公告)日：2013-07-09

申请号：US12032647

申请日：2008-02-16

申请人： Wei-Yi Xiao ,  Michael P. Mullen ,  Vasantha R. Vuyyuru ,  Robert J. Adkins

发明人： Wei-Yi Xiao ,  Michael P. Mullen ,  Vasantha R. Vuyyuru ,  Robert J. Adkins

IPC分类号： G06F17/50

CPC分类号： G06F9/3861 ,  G06F9/455

摘要： A method and apparatus of handling instruction rejects, partial rejects, stalls and branch wrong in a simulation model provides pipeline states for various unit verification. It defines an instruction train to encounter many events of the hardware verifications. Drivers and monitors at a unit and a core simulation level can hook into the pipeline states and perform the verification easily without having to restructure the instructions in the pipeline due to rejects, partial rejects, stalls, branch wrongs. Different event counters have been placed in the instruction pipe during the events and expand the instruction train such that the instruction train provides an accurate and detailed state of each instruction so the hardware logic signals and data can be tracked and identified from each state.

摘要翻译： 在模拟模型中处理指令拒绝，部分拒绝，停顿和分支错误的方法和装置提供用于各种单元验证的流水线状态。 它定义了一个指令列表，以遇到许多硬件验证事件。 单元和核心模拟级别的驱动程序和监视器可以挂钩到管道状态，并且容易地执行验证，而不必由于拒绝，部分拒绝，停顿，分支错误而重新组织管道中的指令。 在事件期间，不同的事件计数器被放置在指令管道中，并扩展指令序列，使得指令串提供每个指令的准确和详细的状态，从而可以从每个状态追踪和识别硬件逻辑信号和数据。

公开(公告)号：US07996203B2

公开(公告)日：2011-08-09

申请号：US12023457

申请日：2008-01-31

申请人： Wei-Yi Xiao ,  Dean G. Bair ,  Christopher A. Krygowski ,  Chung-Lung K. Shum

发明人： Wei-Yi Xiao ,  Dean G. Bair ,  Christopher A. Krygowski ,  Chung-Lung K. Shum

IPC分类号： G06F9/44 ,  G06F13/10 ,  G06F13/12

CPC分类号： G06F9/3851 ,  G06F11/3457 ,  G06F12/0862 ,  G06F2201/885 ,  G06F2212/6026

摘要： A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.

摘要翻译： 提供了一种方法，系统和计算机程序产品，用于在具有多于一个级别的高速缓存层级的处理器设计中验证无序指令地址（IA）跨步预取性能。 产生多个指令流，并将指令循环回相应的指令地址。 将多个指令流调度到处理器和仿真应用程序进行处理。 当调度特定指令时，将特定指令的指令地址和操作数地址记录在队列中。 监视处理器以确定处理器是否根据仿真应用执行提取和预取命令。 检查是否为具有三个或更多步长的指令发出预取命令。

公开(公告)号：US07502725B2

公开(公告)日：2009-03-10

申请号：US10835324

申请日：2004-04-29

申请人： William J. Lewis ,  Wei-Yi Xiao

发明人： William J. Lewis ,  Wei-Yi Xiao

IPC分类号： G06F9/45

CPC分类号： G06F17/5022

摘要： A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.

摘要翻译： 一种在模拟环境中的寄存器管理方法，包括从指令单元解码流水线接收指令。 如果指令是AGI指令，则在仿真环境中执行地址生成互锁（AGI）功能。 执行AGI功能响应于由寄存器管理器和指令控制的寄存器池。 如果指令是早期AGI指令，则在仿真环境中执行早期AGI功能。 执行早期AGI功能可以响应寄存器池和指令。

公开(公告)号：US20080270762A1

公开(公告)日：2008-10-30

申请号：US12164164

申请日：2008-06-30

申请人： William J. Lewis ,  Wei-Yi Xiao

发明人： William J. Lewis ,  Wei-Yi Xiao

IPC分类号： G06F9/30

CPC分类号： G06F17/5022

摘要： A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.

摘要翻译： 一种在模拟环境中的寄存器管理方法，包括从指令单元解码流水线接收指令。 如果指令是AGI指令，则在仿真环境中执行地址生成互锁（AGI）功能。 执行AGI功能响应于由寄存器管理器和指令控制的寄存器池。 如果指令是早期AGI指令，则在仿真环境中执行早期AGI功能。 执行早期AGI功能可以响应寄存器池和指令。

公开(公告)号：US07720669B2

公开(公告)日：2010-05-18

申请号：US12164164

申请日：2008-06-30

申请人： William J. Lewis ,  Wei-Yi Xiao

发明人： William J. Lewis ,  Wei-Yi Xiao

IPC分类号： G06F9/45

CPC分类号： G06F17/5022

摘要： A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.

摘要翻译： 一种在模拟环境中的寄存器管理方法，包括从指令单元解码流水线接收指令。 如果指令是AGI指令，则在仿真环境中执行地址生成互锁（AGI）功能。 执行AGI功能响应于由寄存器管理器和指令控制的寄存器池。 如果指令是早期AGI指令，则在仿真环境中执行早期AGI功能。 执行早期AGI功能可以响应寄存器池和指令。