公开(公告)号：US20080316791A1

公开(公告)日：2008-12-25

申请号：US12191844

申请日：2008-08-14

申请人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

发明人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： H01L27/112 ,  H01L27/11206

摘要： The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.

摘要翻译： 本发明提供一种操作一次性可编程只读存储器（OTPROM）的方法。 OTPROM至少包括设置在基板上的选择晶体管，电极和电介质层，其中电极设置在选择晶体管的源极区域上，电介质层被设置在电极和源极区域之间。 操作一次性可编程只读存储器的方法包括执行编程操作以将数字数据值“1”写入存储器，并执行编程操作以将数字数据值“0”写入存储器。

公开(公告)号：US20070259497A1

公开(公告)日：2007-11-08

申请号：US11778655

申请日：2007-07-17

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： H01L21/336

CPC分类号： G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

摘要翻译： 提供非易失性存储器。 衬底在其中具有至少两个隔离结构以限定有效区域。 一个井位于基板中。 浅掺杂区域位于井中。 至少两个堆叠的栅极结构位于衬底上。 袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。 漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。 辅助栅极层位于堆叠栅极结构之间的衬底上。 栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。 插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

公开(公告)号：US07154142B2

公开(公告)日：2006-12-26

申请号：US11158412

申请日：2005-06-21

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  Y10S438/954

摘要： A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.

摘要翻译： 提供了具有基板，n型阱，p型阱，控制栅极，复合电介质层，源极区域和漏极区域的非易失性存储器件。 在衬底中形成沟槽。 在衬底中形成n型阱。 p型阱形成在n型阱上方的衬底中。 p型阱和n型阱的结点高于沟槽的底部。 突出基板表面的控制栅极形成在沟槽的侧壁上。 复合介质层形成在控制栅极和衬底之间。 复合介电层包括电荷捕获层。 源极区域和漏极区域分别形成在沟槽底部的衬底中，分别在控制栅极的侧面旁边。

公开(公告)号：US20060175652A1

公开(公告)日：2006-08-10

申请号：US11161362

申请日：2005-08-01

申请人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

发明人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

IPC分类号： H01L29/76

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile memory having memory cell columns is provided. Each memory cell column includes many memory cells having a charge-trapping layer and a column select unit. There are no gaps between the memory cells and between the column select unit and the memory cells. A source region and a drain region are disposed in the substrate next to the sides of the serially connected memory cells and column select unit. The selecting lines connect to the gates of the column select unit in the same row. The word lines connect to the gates of the memory cells in the same row. The source lines connect to the source regions in the same row. The sub-bit lines connect to the drain regions in the same column. The main-bit lines connect to the sub-bit lines respectively. The sub-bit line select units are disposed between the sub-bit lines and the main bit lines.

摘要翻译： 提供了具有存储单元列的非易失性存储器。 每个存储单元列包括具有电荷捕获层和列选择单元的许多存储单元。 存储单元之间和列选择单元与存储单元之间没有间隙。 源极区域和漏极区域设置在衬底中，靠近串行连接的存储单元和列选择单元的侧面。 选择线连接到同一行中列选择单元的门。 字线连接到同一行的存储单元的门。 源极线连接到同一行中的源极区域。 子位线连接到同一列中的漏极区。 主位线分别连接到子位线。 子位线选择单元设置在子位线和主位线之间。

公开(公告)号：US20060171206A1

公开(公告)日：2006-08-03

申请号：US11162158

申请日：2005-08-31

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  H01L27/115 ,  H01L27/11521

摘要： A non-volatile memory is provided. A well is disposed in a substrate and a shallow well is disposed inside the well. At least two stack gate structures are disposed on the substrate. Drain regions are disposed in the shallow well outside the stack gate structures. An auxiliary gate layer is disposed on the substrate between the two stack gate structures. The auxiliary gate layer extends down passing through a portion of the substrate. A gate dielectric layer is disposed between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stack gate structures. A conductive plug is disposed on the substrate. The conductive plug extends downward to connect with the shallow well and the drain region therein.

摘要翻译： 提供非易失性存储器。 井被设置在基板中，并且浅井设置在井内。 至少两个堆叠栅极结构设置在基板上。 排水区域设置在堆叠门结构外部的浅井中。 辅助栅极层设置在两个堆叠栅极结构之间的衬底上。 辅助栅极层向下延伸穿过衬底的一部分。 栅极电介质层设置在辅助栅极层和衬底之间以及辅助栅极层和堆叠栅极结构之间。 导电插头设置在基板上。 导电插头向下延伸以与其中的浅孔和漏区连接。

公开(公告)号：US20060145243A1

公开(公告)日：2006-07-06

申请号：US11158412

申请日：2005-06-21

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： H01L21/8242

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  Y10S438/954

摘要： A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.

公开(公告)号：US07335559B2

公开(公告)日：2008-02-26

申请号：US11778655

申请日：2007-07-17

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： H01L21/336

CPC分类号： G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

摘要翻译： 提供非易失性存储器。 衬底在其中具有至少两个隔离结构以限定有效区域。 一个井位于基板中。 浅掺杂区域位于井中。 至少两个堆叠的栅极结构位于衬底上。 袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。 漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。 辅助栅极层位于堆叠栅极结构之间的衬底上。 栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。 插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

公开(公告)号：US20070085124A1

公开(公告)日：2007-04-19

申请号：US11558747

申请日：2006-11-10

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： H01L29/94 ,  H01L21/20 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  Y10S438/954

摘要： A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate, The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.

摘要翻译： 提供了具有基板，n型阱，p型阱，控制栅极，复合电介质层，源极区域和漏极区域的非易失性存储器件。 在衬底中形成沟槽。 n型阱形成在衬底中，p型阱形成在n型阱上方的衬底中。 p型阱和n型阱的结点高于沟槽的底部。 突出基板表面的控制栅极形成在沟槽的侧壁上。 复合介质层形成在控制栅极和衬底之间。 复合介电层包括电荷捕获层。 源极区域和漏极区域分别形成在沟槽底部的衬底中，分别在控制栅极的侧面旁边。

公开(公告)号：US20060186481A1

公开(公告)日：2006-08-24

申请号：US11161312

申请日：2005-07-29

申请人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

发明人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

IPC分类号： H01L29/76

CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A non-volatile memory having many memory cell columns is provided. Each memory cell column includes a plurality of memory cells formed on a substrate. A deep p-type well is disposed in the substrate and an n-type well is disposed on the deep p-type well. A shallow p-type well isolated by device isolation structures is disposed on the n-type well. A select unit is disposed on one side of each memory cell column. An n-type source region is disposed in the substrate adjacent to the select unit. An n-type drain region is disposed in the substrate on the other side of the memory cell column. A bit line is disposed on the substrate. The bit line connects with the n-type drain region through a conductive plug. The conductive plug penetrates the junction between the n-type drain region and the shallow p-type well and forms a short between them.

摘要翻译： 提供了具有许多存储单元列的非易失性存储器。 每个存储单元列包括形成在基板上的多个存储单元。 在衬底中设置深p型阱，在深p型阱上设置n型阱。 通过器件隔离结构隔离的浅P型阱设置在n型阱上。 选择单元设置在每个存储单元列的一侧。 n型源极区域设置在与选择单元相邻的衬底中。 在存储单元列的另一侧的衬底中设置n型漏极区。 位线设置在基板上。 位线通过导电插头与n型漏极区域连接。 导电插塞穿透n型漏极区和浅P型阱之间的结，并在它们之间形成短路。

公开(公告)号：US20060170026A1

公开(公告)日：2006-08-03

申请号：US11162116

申请日：2005-08-29

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

摘要翻译： 提供非易失性存储器。 衬底在其中具有至少两个隔离结构以限定有效区域。 一个井位于基板中。 浅掺杂区域位于井中。 至少两个堆叠的栅极结构位于衬底上。 袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。 漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。 辅助栅极层位于堆叠栅极结构之间的衬底上。 栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。 插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。