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    Multi-level amplitude signaling receiver
    1.
    发明授权
    Multi-level amplitude signaling receiver 有权
    多电平振幅信号接收机

    公开(公告)号：US08750406B2

    公开(公告)日：2014-06-10

    申请号：US13363098

    申请日：2012-01-31

    申请人： Mingde Pan ,  Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Masashi Shimanouchi

    发明人： Mingde Pan ,  Weiqi Ding ,  Sergey Shumarayev ,  Peng Li ,  Masashi Shimanouchi

    IPC分类号： H04L25/34 ,  H04L25/49

    CPC分类号： H04L25/4917 ,  H03D1/00 ,  H04L25/066 ,  H04L27/06

    摘要： One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及用于多电平振幅信令的接收机电路，其包括用于每个符号周期的至少三个幅度电平。 接收器电路包括峰值检测器，参考电压发生器和比较器电路。 峰值检测器被设置为检测多电平幅度信号的峰值电压，并且参考电压发生器使用峰值电压来产生多个参考电压。 比较器电路使用多个参考电压来检测多电平幅度信号的幅度电平。 还公开了其它实施例和特征。

    On-chip full eye viewer architecture
    2.
    发明授权
    On-chip full eye viewer architecture 有权
    片上全景查看器架构

    公开(公告)号：US08451883B1

    公开(公告)日：2013-05-28

    申请号：US12630674

    申请日：2009-12-03

    申请人： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

    发明人： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

    IPC分类号： H04B3/46

    CPC分类号： G01R31/3171 ,  H04L1/0061 ,  H04L1/203 ,  H04L1/205 ,  H04L1/248 ,  H04L7/033 ,  H04L7/0334 ,  H04L7/048

    摘要： Systems, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with an equalized serial input signal. The device may include an equalizer and eye viewer circuitry. The equalizer may receive and perform equalization on a serial input signal to produce the equalized serial input signal, and the eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the equalized serial input signal.

    摘要翻译： 提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和装置。 例如，集成电路设备的一个实施例可能能够确定与均衡的串行输入信号相关联的眼图。 该装置可以包括均衡器和眼睛观察器电路。 均衡器可以在串行输入信号上接收和执行均衡以产生均衡的串行输入信号，并且眼睛观察器电路可以确定与均衡的串行输入信号相关联的眼图的水平和垂直边界。

    Bit error rate checker receiving serial data signal from an eye viewer
    3.
    发明授权
    Bit error rate checker receiving serial data signal from an eye viewer 有权
    位错误率检测器从眼睛观察器接收串行数据信号

    公开(公告)号：US08433958B2

    公开(公告)日：2013-04-30

    申请号：US12884923

    申请日：2010-09-17

    申请人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

    发明人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

    IPC分类号： G06F11/00

    CPC分类号： H04L1/203 ,  G01R31/3171

    摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

    摘要翻译： 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

    On-chip data signal eye monitoring circuitry and methods
    4.
    发明授权
    On-chip data signal eye monitoring circuitry and methods 有权
    片上数据信号眼监测电路及方法

    公开(公告)号：US08111784B1

    公开(公告)日：2012-02-07

    申请号：US12082483

    申请日：2008-04-11

    申请人： Weiqi Ding ,  Mingde Pan ,  Wilson Wong ,  Sergey Shumarayev ,  Peng Li

    发明人： Weiqi Ding ,  Mingde Pan ,  Wilson Wong ,  Sergey Shumarayev ,  Peng Li

    IPC分类号： H04L25/06

    CPC分类号： H04L25/063

    摘要： Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.

    摘要翻译： 用于收集关于高速串行数据信号的眼睛的信息的方法和装置包括在几个眼睛切片位置采样重复的多位数据模式的每一位。 对于任何给定的眼片位置，将数据模式中的每个位在电压中与基线参考信号电压进行比较，以建立该位的参考值。 然后在重复电压比较时，参考信号电压逐渐增加，直到比较结果的一些位与该位的参考值不同。 这在眼部切片位置建立了眼睛的上限值。 然后，参考信号电压逐渐减小，以类似地找到该眼片的较低值。

    On-chip eye viewer architecture for highspeed transceivers
    5.
    发明授权
    On-chip eye viewer architecture for highspeed transceivers 有权
    用于高速收发器的片上眼睛查看器架构

    公开(公告)号：US08744012B1

    公开(公告)日：2014-06-03

    申请号：US13369108

    申请日：2012-02-08

    申请人： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

    发明人： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

    IPC分类号： H03K9/00

    CPC分类号： H04L1/203 ,  G01R31/31711

    摘要： System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.

    摘要翻译： 提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和设备。 例如，集成电路器件的一个实施例可能能够在均衡期间或之后确定与串行输入信号相关联的眼图。 该装置可以包括均衡器和眼睛观察器电路，其被配置为选择均衡器的节点，用于在均衡期间或之后的输入信号的眼睛监视。 在一个实施例中，眼睛观察器电路可以为每个相应节点提供单独的采样器，同时在采样器之间共享控制逻辑和相位插值器。 从均衡器的选定节点看，眼睛观察器电路可以确定与串行输入信号相关联的眼图的水平和垂直边界。

    Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations
    6.
    发明授权
    Circuitry on an integrated circuit for performing or facilitating oscilloscope, jitter, and/or bit-error-rate tester operations 有权
    用于执行或促进示波器，抖动和/或误码率测试仪操作的集成电路的电路

    公开(公告)号：US08504882B2

    公开(公告)日：2013-08-06

    申请号：US12884305

    申请日：2010-09-17

    申请人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

    发明人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Siriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

    IPC分类号： G06F11/00

    CPC分类号： G06F11/267

    摘要： An integrated circuit (“IC”) includes circuitry for use in testing a serial data signal. One such IC includes circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. One such IC also includes circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. Such an IC provides output signals indicative of results of its operations. One such IC operates in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

    摘要翻译： 集成电路（“IC”）包括用于测试串行数据信号的电路。 一个这样的IC包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度来发送串行数据信号的电路。 一个这样的IC还包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 这样的IC提供指示其操作结果的输出信号。 一个这样的IC以各种模式运行，以执行或至少模拟示波器，误码率测试仪等的功能，用于测试关于抖动容差，噪声容限等的信号和电路。

    BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER
    7.
    发明申请
    BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER 有权
    从眼睛观察器接收串行数据信号的位错误率检查器

    公开(公告)号：US20120072785A1

    公开(公告)日：2012-03-22

    申请号：US12884923

    申请日：2010-09-17

    申请人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

    发明人： Weiqi Ding ,  Mingde Pan ,  Peng Li ,  Sergey Shumarayev ,  Masashi Shimanouchi

    IPC分类号： G06F11/00

    CPC分类号： H04L1/203 ,  G01R31/3171

    摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

    摘要翻译： 提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。 在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。 在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。 在一个实现中，BER检查器是专用的BER检查器。 在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

    CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS
    8.
    发明申请
    CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS 有权
    用于执行或促进OSCILLOSCOPE，JITTER和/或BIT错误率测试仪操作的集成电路的电路

    公开(公告)号：US20120072784A1

    公开(公告)日：2012-03-22

    申请号：US12884305

    申请日：2010-09-17

    申请人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

    发明人： Peng Li ,  Masashi Shimanouchi ,  Sergey Shumarayev ,  Weiqi Ding ,  Sriram Narayan ,  Daniel Tun Lai Chow ,  Mingde Pan

    IPC分类号： G06F11/00

    CPC分类号： G06F11/267

    摘要： An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

    摘要翻译： 集成电路（“IC”）可以包括用于测试串行数据信号的电路。 IC可以包括用于以可选的抖动，可选的噪声和/或可控地变化的驱动强度发送串行数据信号的电路。 IC还可以包括用于接收串行数据信号并且在这种信号中执行误码率（“BER”）分析的电路。 IC可以提供指示其操作结果的输出信号。 IC可以以各种模式运行，以执行或至少模拟示波器，误码率测试仪等功能，用于在抖动容限，噪声容限等方面测试信号和电路。

    On-die jitter generator
    9.
    发明授权
    On-die jitter generator 有权
    裸片抖动发生器

    公开(公告)号：US09222972B1

    公开(公告)日：2015-12-29

    申请号：US12884747

    申请日：2010-09-17

    申请人： Weiqi Ding ,  Sergey Shumarayev ,  Mingde Pan ,  Peng Li ,  Masashi Shimanouchi

    发明人： Weiqi Ding ,  Sergey Shumarayev ,  Mingde Pan ,  Peng Li ,  Masashi Shimanouchi

    IPC分类号： G01R31/02 ,  G01R31/317

    CPC分类号： G01R31/31709

    摘要： An IC that includes a jitter generator, where the jitter generator is integral with the IC and generates non-intrinsic jitter, is provided. In one implementation, the non-intrinsic jitter is used to measure a characteristic of the IC. In one implementation, the non-intrinsic jitter is used to test jitter tolerance of the IC. In yet another implementation, the non-intrinsic jitter is used to test another IC coupled to the IC that includes the jitter generator.

    摘要翻译： 提供了包括抖动发生器的IC，其中抖动发生器与IC集成并产生非固有抖动。 在一个实现中，非固有抖动用于测量IC的特性。 在一个实现中，非固有抖动用于测试IC的抖动容限。 在又一实现中，使用非固有抖动来测试耦合到包括抖动发生器的IC的另一IC。

    Equalizer circuitry with selectable tap positions and coefficients
    10.
    发明授权
    Equalizer circuitry with selectable tap positions and coefficients 有权
    均衡器电路，具有可选择的抽头位置和系数

    公开(公告)号：US08705602B1

    公开(公告)日：2014-04-22

    申请号：US12580587

    申请日：2009-10-16

    申请人： Weiqi Ding ,  Mengchi Liu ,  Mingde Pan ,  Thungoc M. Tran ,  Sergey Shumarayev

    发明人： Weiqi Ding ,  Mengchi Liu ,  Mingde Pan ,  Thungoc M. Tran ,  Sergey Shumarayev

    IPC分类号： H03H7/30 ,  H03H7/40

    CPC分类号： H04L25/03038 ,  H04L25/03343

    摘要： Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).

    摘要翻译： 例如，用于串行数字数据信号的发射机均衡器电路包括用于输出通过延迟线电路传播的信号的多个不同延迟版本的抽头延迟线电路。 均衡器电路还包括多个电流数模转换器（“DAC”）。 均衡器电路还包括可控（例如，可编程）路由电路，用于可选地将信号的延迟版本路由到各​​种DAC。 各种DAC所使用的电流强度也优选是可控的（例如，可编程的）。