公开(公告)号：US20050233495A1

公开(公告)日：2005-10-20

申请号：US10859764

申请日：2004-06-03

申请人： Tsung-Hsi Yang ,  Chung-Liang Lee ,  Chu-Shou Yang ,  Guangli Luo ,  Wu-Ching Chou ,  Chun-Yen Chang ,  Tsung-Yeh Yang

发明人： Tsung-Hsi Yang ,  Chung-Liang Lee ,  Chu-Shou Yang ,  Guangli Luo ,  Wu-Ching Chou ,  Chun-Yen Chang ,  Tsung-Yeh Yang

IPC分类号： C30B23/08 ,  C23C14/06 ,  C23C16/30 ,  C30B23/02 ,  C30B29/48 ,  C30B29/52 ,  H01L21/00 ,  H01L21/06 ,  H01L21/10 ,  H01L21/203 ,  H01L21/205 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/365 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L31/0296 ,  C30B23/02 ,  C30B29/48 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0256 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02631 ,  H01L33/0087

摘要： A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1-x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers. Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1-x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.

摘要翻译： 提供了在Si衬底上生长高质量和大面积ZnSe层的技术，其包括在Si衬底上生长Ge x Si x Si 1-x / Ge外延层， 高真空化学气相沉积（UHVCVD），最后在顶部Ge缓冲层上生长ZnSe膜。 在本发明的方法中应用了两个概念，第一个概念是为了阻止由Ge x 1 Si 1-x N外延层产生的位错并终止传播的向上位错 通过使用应变界面，ZnSe层的位错密度大大降低，表面粗糙度提高; 第二个概念是解决极性材料在非极性材料上使用偏角Si衬底生长的反相域问题，并且在不同原子之间没有扩散问题，而在Si衬底上通常生长ZnSe层 。

公开(公告)号：US07777267B2

公开(公告)日：2010-08-17

申请号：US11969119

申请日：2008-01-03

申请人： Erik S Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

发明人： Erik S Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

IPC分类号： H01L29/94

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

摘要： The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

摘要翻译： 非易失性存储器的制造方法及其结构通过在基底上构建栅极介电层来实现。 栅极电介质包含至少两层不同的材料层。 至少一个杂质元素种植在栅介电层的顶部，以增加电子阱密度。 然后在去除最上层的材料之后重建一个新的顶部材料。 最后，在栅极电介质层上形成栅极电极层，并在栅极电介质层的两侧的基部形成源极/漏极。 在本发明中，随着异质元素的种植，它将在栅电介质层中形成陷阱，其可以更容易地捕获电子。 因此，电子不会随着操作时间的增加而结合在一起。 可以有效地延长存储时间，并且可以解决叮咬的组合问题。

公开(公告)号：US20080150048A1

公开(公告)日：2008-06-26

申请号：US11969119

申请日：2008-01-03

申请人： Erik S. Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

发明人： Erik S. Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

IPC分类号： H01L29/792

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

摘要： The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of4terial. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

摘要翻译： 非易失性存储器的制造方法及其结构通过在基底上构建栅极介电层来实现。 栅极电介质包含至少两层不同的材料层。 至少一个杂质元素种植在栅介电层的顶部，以增加电子阱密度。 然后在删除最上层的四层后重建一个新的顶层材料。 最后，在栅极电介质层上形成栅极电极层，并在栅极电介质层的两侧的基部形成源极/漏极。 在本发明中，随着异质元素的种植，它将在栅电介质层中形成陷阱，其可以更容易地捕获电子。 因此，电子不会随着操作时间的增加而结合在一起。 可以有效地延长存储时间，并且可以解决叮咬的组合问题。

公开(公告)号：US07071087B2

公开(公告)日：2006-07-04

申请号：US10859764

申请日：2004-06-03

申请人： Tsung-Hsi Yang ,  Chung-Liang Lee ,  Chu-Shou Yang ,  Guangli Luo ,  Wu-Ching Chou ,  Chun-Yen Chang ,  Tsung-Yeh Yang

发明人： Tsung-Hsi Yang ,  Chung-Liang Lee ,  Chu-Shou Yang ,  Guangli Luo ,  Wu-Ching Chou ,  Chun-Yen Chang ,  Tsung-Yeh Yang

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L31/0296 ,  C30B23/02 ,  C30B29/48 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0256 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/02631 ,  H01L33/0087

摘要： A technique to grow high quality and large area ZnSe layer on Si substrate is provided, comprising growing GexSi1−x/Ge epitaxial layers on Si substrate by using ultra-high vacuum chemical vapor deposition (UHVCVD), and finally growing a ZnSe film on top Ge buffer layers.Two concepts are applied in the process of this invention, the first one is to block the dislocations generated from GexSi1−x epitaxial layers and to terminate the propagated upward dislocations by using strained interfaces, accordingly the dislocation density of ZnSe layer is greatly reduced and the surface roughness is improved; the second concept is to solve the problems of anti-phase domain due to growth of polar materials on non-polar material using off-cut angle Si substrate, and that is free from diffusion problems between different atoms while generally growing ZnSe layers on Si substrate.

摘要翻译： 提供了在Si衬底上生长高质量和大面积ZnSe层的技术，其包括在Si衬底上生长Ge x Si x Si 1-x / Ge外延层， 高真空化学气相沉积（UHVCVD），最后在顶部Ge缓冲层上生长ZnSe膜。 在本发明的方法中应用了两个概念，第一个概念是为了阻止由Ge x 1 Si 1-x N外延层产生的位错并终止传播的向上位错 通过使用应变界面，ZnSe层的位错密度大大降低，表面粗糙度提高; 第二个概念是解决极性材料在非极性材料上使用偏角Si衬底生长的反相域问题，并且在不同原子之间没有扩散问题，而在Si衬底上通常生长ZnSe层 。

公开(公告)号：US20050156228A1

公开(公告)日：2005-07-21

申请号：US10758132

申请日：2004-01-16

申请人： Erik Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

发明人： Erik Jeng ,  Wu-Ching Chou ,  Chih-Hsueh Hung ,  Chien-Cheng Li

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/513 ,  H01L29/40117 ,  H01L29/517 ,  H01L29/518 ,  H01L29/792

摘要： The manufacturing method of a nonvolatile memory and its structure is achieved by building a gate dielectric layer on a base. The gate dielectric layer contains at least two layers of different material layers. At least one hetero element is planted on the top of the gate dielectric layer so as to increase the electronic trap density. Then rebuild a new top material after removing the upmost layer of material. Finally, build a gate electrode layer on the gate dielectric layer and form source/drain electrodes at the bases of both sides of the gate dielectric layer. In this invention, with the planting of the hetero element, it will form traps in the gate dielectric layer that can catch electrons more easily. Thus, the electrons won't combine together with the increase of operation time. The storage time can be effectively extended and the problem of the combination of bites can be solved.

摘要翻译： 非易失性存储器的制造方法及其结构通过在基底上构建栅极介电层来实现。 栅介质层包含至少两层不同的材料层。 至少一个杂质元素种植在栅介电层的顶部，以增加电子阱密度。 然后在去除最上层的材料之后重建一个新的顶部材料。 最后，在栅极电介质层上形成栅极电极层，并在栅极电介质层的两侧的基部形成源极/漏极。 在本发明中，随着异质元素的种植，它将在栅电介质层中形成陷阱，其可以更容易地捕获电子。 因此，电子不会随着操作时间的增加而结合在一起。 可以有效地延长存储时间，并且可以解决叮咬的组合问题。

公开(公告)号：US20060029792A1

公开(公告)日：2006-02-09

申请号：US11005547

申请日：2004-12-06

申请人： Wei-Kuo Chen ,  Ming-Chih Lee ,  Wu-Ching Chou ,  Wen-Hsiung Chen ,  Wen-Cheng Ke

发明人： Wei-Kuo Chen ,  Ming-Chih Lee ,  Wu-Ching Chou ,  Wen-Hsiung Chen ,  Wen-Cheng Ke

IPC分类号： B05D7/00 ,  C23C16/00 ,  B32B5/16

CPC分类号： C30B29/406 ,  B82Y10/00 ,  B82Y30/00 ,  C30B25/00 ,  C30B25/14 ,  C30B29/40 ,  C30B29/48 ,  C30B29/52 ,  C30B29/605 ,  Y10T428/25

摘要： Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

摘要翻译： 在没有掩模制造并允许任何程度的晶格失配的情况下在缓冲层上制造自组装纳米颗粒的方法; 即包含III-V族，II-VI族或IV-VI族的二元，三元或四元纳米颗粒。 该方法包括施加缓冲层的第一步骤，打开吹扫气体以将第一反应物调节到较低的第一流速的第二步骤，然后将第二反应物供应到缓冲层以形成富金属的岛 以及再次打开吹扫气体以将第一反应物调节到较高的第二流量的缓冲层上的第三步骤。 在富金属的岛上形成二元，三元或四元III-V，II-VI和IV-IV半导体材料的纳米颗粒。 然后在高温下在第一反应物流下重结晶形成高质量的纳米颗粒。

公开(公告)号：US20110108797A1

公开(公告)日：2011-05-12

申请号：US12628165

申请日：2009-11-30

申请人： Chu-Shou Yang ,  Chia-Sing Wu ,  Wu-Ching Chou ,  Mei-Tsao Chiang ,  Chi-Neng Mo ,  Chih-Wei Luo ,  Liang-Kuei Huang

发明人： Chu-Shou Yang ,  Chia-Sing Wu ,  Wu-Ching Chou ,  Mei-Tsao Chiang ,  Chi-Neng Mo ,  Chih-Wei Luo ,  Liang-Kuei Huang

IPC分类号： H01L33/00

CPC分类号： H01L33/08 ,  H01L33/28

摘要： A single chip type white light LED device includes a first semiconductor layer of a first doping type, a ZnMnSeTe (Zinc Manganese Selenium Tellurium) red light quantum well, a first barrier layer disposed on the ZnMnSeTe red light quantum well, a green light emitting layer including green light quantum dots disposed on the first barrier layer, a second barrier layer disposed on the green light emitting layer, a blue light emitting layer including blue light quantum dots disposed on the second barrier layer, a third barrier layer disposed on the blue light emitting layer, and a second semiconductor layer disposed on the third barrier layer.

摘要翻译： 单芯片型白光LED器件包括第一掺杂类型的第一半导体层，ZnMnSeTe（锌锰硒碲）红光量子阱，设置在ZnMnSeTe红光量子阱上的第一势垒层，绿色发光层 包括设置在第一阻挡层上的绿光量子点，设置在绿色发光层上的第二阻挡层，设置在第二阻挡层上的包含蓝色光量子点的蓝色发光层，设置在蓝色光上的第三阻挡层 发光层和设置在第三阻挡层上的第二半导体层。

公开(公告)号：US07294202B2

公开(公告)日：2007-11-13

申请号：US11005547

申请日：2004-12-06

申请人： Wei-Kuo Chen ,  Ming-Chih Lee ,  Wu-Ching Chou ,  Wen-Hsiung Chen ,  Wen-Cheng Ke

发明人： Wei-Kuo Chen ,  Ming-Chih Lee ,  Wu-Ching Chou ,  Wen-Hsiung Chen ,  Wen-Cheng Ke

IPC分类号： C30B29/60

CPC分类号： C30B29/406 ,  B82Y10/00 ,  B82Y30/00 ,  C30B25/00 ,  C30B25/14 ,  C30B29/40 ,  C30B29/48 ,  C30B29/52 ,  C30B29/605 ,  Y10T428/25

摘要： Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.

摘要翻译： 在没有掩模制造并允许任何程度的晶格失配的情况下在缓冲层上制造自组装纳米颗粒的方法; 即包含III-V族，II-VI族或IV-VI族的二元，三元或四元纳米颗粒。 该方法包括施加缓冲层的第一步骤，打开吹扫气体以将第一反应物调节到较低的第一流速的第二步骤，然后将第二反应物供应到缓冲层以形成富金属的岛 以及再次打开吹扫气体以将第一反应物调节到较高的第二流量的缓冲层上的第三步骤。 在富金属的岛上形成二元，三元或四元III-V，II-VI和IV-IV半导体材料的纳米颗粒。 然后在高温下在第一反应物流下重结晶形成高质量的纳米颗粒。

公开(公告)号：US20060019441A1

公开(公告)日：2006-01-26

申请号：US10891373

申请日：2004-07-14

申请人： Erik Jeng ,  Wu-Ching Chou ,  Li-Kang Wu ,  Chien-Chen Li

发明人： Erik Jeng ,  Wu-Ching Chou ,  Li-Kang Wu ,  Chien-Chen Li

IPC分类号： H01L21/8238

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/4234

摘要： A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that electrons can be prevented from binding together as the operation time increased; etching off both ends of the original upper and underlying oxide layers to reduce the structural destruction caused by the implantation of heterogeneous elements; and finally, depositing an oxide gate interstitial wall to eradicate electron loss and hence promote the reliability of the device.

摘要翻译： 通过倾斜角度离子注入制造非易失性存储器的方法基本上包括以下步骤：在氮化物电介质层中注入异质元素，例如Ge，Si，N 2，O 2等，以形成能够捕获的阱 在氮化物电介质层内捕获更多的电子，使得当操作时间增加时可以防止电子结合在一起; 蚀刻原始上部和下部氧化物层的两端以减少由异质元素的注入引起的结构破坏; 最后，沉积氧化物栅间隙壁以消除电子损失，从而提高器件的可靠性。

公开(公告)号：US07179708B2

公开(公告)日：2007-02-20

申请号：US10891373

申请日：2004-07-14

申请人： Erik S. Jeng ,  Wu-Ching Chou ,  Li-Kang Wu ,  Chien-Chen Li

发明人： Erik S. Jeng ,  Wu-Ching Chou ,  Li-Kang Wu ,  Chien-Chen Li

IPC分类号： H01L21/336

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/4234

摘要： A process for fabricating non-volatile memory by tilt-angle ion implantation comprises essentially the steps of implanting sideling within a nitride dielectric layer heterogeneous elements such as, for example, Ge, Si, N2, O2, and the like, for forming traps capable of capturing more electrons within the nitride dielectric layer such that electrons can be prevented from binding together as the operation time increased; etching off both ends of the original upper and underlying oxide layers to reduce the structural destruction caused by the implantation of heterogeneous elements; and finally, depositing an oxide gate interstitial wall to eradicate electron loss and hence promote the reliability of the device.

摘要翻译： 通过倾斜角度离子注入制造非易失性存储器的方法基本上包括以下步骤：在氮化物电介质层中注入异质元素，例如Ge，Si，N 2，O 2等，以形成能够捕获的阱 在氮化物电介质层内捕获更多的电子，使得当操作时间增加时可以防止电子结合在一起; 蚀刻原始上部和下部氧化物层的两端以减少由异质元素的注入引起的结构破坏; 最后，沉积氧化物栅间隙壁以消除电子损失，从而提高器件的可靠性。