公开(公告)号：US20100238157A1

公开(公告)日：2010-09-23

申请号：US12569186

申请日：2009-09-29

申请人： Weon-Jun CHOE ,  Ah-Reum KIM ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG ,  Do-Hwan OH ,  Hee-Soo SONG

发明人： Weon-Jun CHOE ,  Ah-Reum KIM ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG ,  Do-Hwan OH ,  Hee-Soo SONG

IPC分类号： G09G5/00 ,  H04L27/06

CPC分类号： G09G3/20 ,  G09G3/3648 ,  G09G2310/08 ,  G09G2370/08 ,  H03K7/04

摘要： A method of modulating and demodulating a signal includes modulating data information included in an input data signal provided from an external source and clock information included in an input clock signal provided from the external source into a transmission signal, using (n+1) delay clock signals generated based on the input clock signal, where n is a natural number. The transmission signal is demodulated into an output clock signal including restored clock information and an output data signal including restored data information, using (m+1) delay clock signals generated based on the clock information, where m is a natural number less than n.

摘要翻译： 调制和解调信号的方法包括：使用（n + 1）个延迟时钟将从外部源提供的输入数据信号中包括的数据信息和从外部源提供的输入时钟信号中包括的时钟信息调制成发送信号 基于输入时钟信号生成的信号，其中n是自然数。 使用基于时钟信息生成的（m + 1）个延迟时钟信号，将发送信号解调为包括恢复的时钟信息的输出时钟信号和包括恢复的数据信息的输出数据信号，其中m是小于n的自然数。

公开(公告)号：US20100156550A1

公开(公告)日：2010-06-24

申请号：US12630885

申请日：2009-12-04

申请人： Do-hwan OH ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG

发明人： Do-hwan OH ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG

IPC分类号： H03L7/02 ,  H01G4/40

CPC分类号： H03L7/099 ,  H03J2200/10 ,  H03L7/18 ,  H03L2207/06 ,  H03L2207/50

摘要： An adjustable capacitor is provided including a capacitor unit including a plurality of capacitor groups aligned in a matrix format and a switch unit to adjust capacitance by connecting the plurality of capacitor groups in parallel according to a selection signal of a column and row of the matrix. Accordingly, the adjustable capacitor may be realized of a small size but with a high capacitance change rate.

摘要翻译： 提供了一种可调节电容器，包括：电容器单元，其包括以矩阵形式排列的多个电容器组;以及开关单元，用于根据矩阵的列和行的选择信号并联连接多个电容器组来调整电容。 因此，可调电容器可以实现为小尺寸但具有高电容变化率。

公开(公告)号：US20100134165A1

公开(公告)日：2010-06-03

申请号：US12627229

申请日：2009-11-30

申请人： Do-hwan OH ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG

发明人： Do-hwan OH ,  Kyo-Jin CHOO ,  Deog-Kyoon JEONG

IPC分类号： H03L7/06 ,  H03K5/13

CPC分类号： G04F10/005 ,  G04F10/06 ,  H03L7/087 ,  H03L7/091

摘要： A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.

摘要翻译： 时间数字转换器（TDC）包括接收第一信号和第二信号的转换器，使用串联耦合的多个延迟元件来相位延迟第二信号，将延迟的第二信号与第一信号进行比较 并且输出相对于第一信号的第二信号的相位误差，接收第一信号的相位频率检测器和来自多个延迟元件中的一个节点的第三信号，并且输出第二信号之间的相位差 第一信号和第三信号，以及频率检测器，其使用相位频率检测器和第二信号的输出信号将相对于第一信号的第二信号的频率误差作为数字码输出。

公开(公告)号：US20080252504A1

公开(公告)日：2008-10-16

申请号：US11926503

申请日：2007-10-29

申请人： Deog-Kyoon JEONG ,  Weon Jun Choe

发明人： Deog-Kyoon JEONG ,  Weon Jun Choe

IPC分类号： H03M1/66

CPC分类号： H03M1/1019 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2320/0209 ,  G09G2330/026 ,  H03M1/662

摘要： A technique for removing vertical stripe artifacts generated in a Liquid Crystal Display (LCD) panel, more particularly a technique for compensating for and removing an inter-channel offset voltage of a column driver, which causes the vertical stripe artifacts, is disclosed. An offset voltage generated in each channel for driving each pixel of the LCD panel is detected for a whole signal path and offset voltages detected for all channels are compared and extracted according to a given timing sequence by a common signal comparator, thereby preventing the offset of the detection comparator and reducing a chip size of the column driver in contrary to the prior art. Moreover, an inter-channel offset voltage is detected in a digital circuit mode, thereby compensating for process variations in a semiconductor chip manufacturing process in circuit terms.

摘要翻译： 公开了一种用于去除在液晶显示器（LCD）面板中产生的垂直条纹伪像的技术，更具体地说，一种用于补偿和去除导致垂直条纹伪影的列驱动器的通道间偏移电压的技术。 针对整个信号路径检测用于驱动LCD面板的每个像素的每个通道中产生的偏移电压，并且通过公共信号比较器根据给定的定时序列来对所有通道检测到的偏移电压进行比较和提取，从而防止 检测比较器并且与现有技术相反地减小列驱动器的芯片尺寸。 此外，以数字电路模式检测信道间偏移电压，从而以电路方式补偿半导体芯片制造工艺中的工艺变化。

公开(公告)号：US20090313410A1

公开(公告)日：2009-12-17

申请号：US12477545

申请日：2009-06-03

申请人： Deog-Kyoon JEONG ,  Suhwan KIM ,  Woo-Yeol SHIN ,  Dong-Hyuk LIM ,  Ic-Su OH

发明人： Deog-Kyoon JEONG ,  Suhwan KIM ,  Woo-Yeol SHIN ,  Dong-Hyuk LIM ,  Ic-Su OH

IPC分类号： G06F13/00

CPC分类号： G06F13/4086

摘要： A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.

摘要翻译： 总线系统包括多个短截线; 多个连接器，每个连接器串联耦合在相应的一个短截线和相应的一个存储器模块之间; 多个第一串联负载，每个第一串联负载串联耦合到对应的一个连接器; 以及多个第二串联负载，每个第二串联负载串联耦合到相应一个短截线的传输线的特征阻抗，其中第一和第二串联负载被确定为在 存根