公开(公告)号：US20200005875A1

公开(公告)日：2020-01-02

申请号：US16020742

申请日：2018-06-27

Applicant: Western Digital Technologies, Inc.

Inventor： Niles Yang ,  Pitamber Shukla

IPC: G11C16/16 ,  G11C16/34 ,  G11C29/00 ,  G11C29/52 ,  G06F11/10

Abstract: Dynamic modification of health metrics for data blocks in non-volatile storage media based on erase operation loop counts. In one implementation, a method includes iteratively erasing a block of non-volatile storage media until a count of non-erasable bits satisfies criteria comprising an allowable non-erasable bits parameter, and determining that a number of iterations needed to erase the block exceeds a threshold number of iterations. The method further includes, in response to the number of iterations exceeding the threshold number of iterations, increasing the allowable non-erasable bits parameter for a subsequent erasure of the block.

公开(公告)号：US10460814B2

公开(公告)日：2019-10-29

申请号：US15838863

申请日：2017-12-12

Applicant: Western Digital Technologies, Inc.

Inventor： Piyush Dak ,  Mohan Vamsi Dunga ,  Pitamber Shukla

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/408 ,  G11C7/12 ,  G06F3/06 ,  G11C11/4097

Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.

公开(公告)号：US10790031B1

公开(公告)日：2020-09-29

申请号：US16432116

申请日：2019-06-05

Applicant: Western Digital Technologies, Inc.

Inventor： Piyush Sagdeo ,  Chris Yip ,  Sourabh Sankule ,  Pitamber Shukla ,  Anubhav Khandelwal ,  Mohan Dunga ,  Niles Yang

IPC: G11C16/34 ,  G11C29/50 ,  G06F11/07

Abstract: A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.

公开(公告)号：US10354736B1

公开(公告)日：2019-07-16

申请号：US15966724

申请日：2018-04-30

Applicant: Western Digital Technologies, Inc.

Inventor： Nian Niles Yang ,  Pitamber Shukla

IPC: G11C16/04 ,  G11C16/34 ,  G06F11/07 ,  G06F11/00 ,  G11C16/14

Abstract: The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an uncertainty prediction circuit coupled to the memory cells, and a data conversion circuit coupled to the memory cells. The uncertainty prediction circuit is configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state. The data conversion circuit is configured to apply a data conversion to a portion of data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.

公开(公告)号：US10755798B2

公开(公告)日：2020-08-25

申请号：US16221682

申请日：2018-12-17

Applicant: Western Digital Technologies, Inc.

Inventor： Niles Yang ,  Pitamber Shukla ,  Mohan Dunga

IPC: G11C11/56 ,  G11C29/52 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G11C11/4074 ,  G11C11/4099 ,  G11C16/28

Abstract: Recovering data from a faulty memory block in a memory system. Various methods include: reading a target word line in a memory block to obtain a first data; determining the first data has an uncorrectable error; and then adjust bias parameters of a first group of neighboring word lines within the memory block, where adjusting bias parameters creates a first adjusted bias parameters; and reading the target word line using the adjusted bias parameters to obtain second data from the target word line. The method also includes determining the second data has a second uncorrectable error; and then adjusting bias parameters of a second group of lines within the memory block, where adjusting the bias parameters of the second group creates second adjusted bias parameters; and reading the target word line using the first and second adjusted bias parameters to obtain a third data from the target word line.

公开(公告)号：US10559366B2

公开(公告)日：2020-02-11

申请号：US15941747

申请日：2018-03-30

Applicant: Western Digital Technologies, Inc.

Inventor： Zhenlei Shen ,  Pitamber Shukla ,  Philip Reusswig ,  Niles N. Yang ,  Anubhav Khandelwal

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C29/50 ,  G11C16/26

Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.