公开(公告)号：US08428207B1

公开(公告)日：2013-04-23

申请号：US12957262

申请日：2010-11-30

申请人： William Dally ,  Stephen G. Tell

发明人： William Dally ,  Stephen G. Tell

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H04L7/0012 ,  H04L7/005

摘要： A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

摘要翻译： 提供了一种用于确定对时钟域的信号进行安全采样的时间的系统和方法。 在一个实施例中，使用频率估计器来计算第一时钟域的频率估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用频率估计由第二时钟域安全地采样。 在另一实施例中，使用频率估计器来计算第一时钟域的频率估计。 此外，利用相位估计器，基于频率估计来计算第一时钟域的相位估计。 此外，确定来自第一时钟域的信号不变的时间，使得信号能够使用相位估计被第二时钟域安全地采样。

公开(公告)号：US07817767B2

公开(公告)日：2010-10-19

申请号：US11021975

申请日：2004-12-23

申请人： Stephen G. Tell ,  Thomas H. Greer, III

发明人： Stephen G. Tell ,  Thomas H. Greer, III

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/0814 ,  H03L7/093 ,  H03L2207/50 ,  H04L7/0025 ,  H04L7/0331 ,  H04L7/0337

摘要： A processor-controlled clock-data recovery (CDR) system. Phase error signals having either a first state or a second state are generated within the CDR system according to whether a first clock signal leads or lags transitions of a data signal. A difference value is generated based on the phase error signals, the difference value indicating a difference between the number of the phase error signals having the first state and a number of the phase error signals having the second state. The difference value is transferred to a processor which is programmed to determine whether the difference value exceeds a first threshold and, if so, to adjust the phase of the first clock signal.

摘要翻译： 处理器控制的时钟数据恢复（CDR）系统。 根据第一时钟信号是否导致或滞后数据信号的转换，在CDR系统内产生具有第一状态或第二状态的相位误差信号。 基于相位误差信号产生差值，该差值表示具有第一状态的相位误差信号的数量与具有第二状态的相位误差信号的数量之间的差异。 差分值被传送到处理器，该处理器被编程以确定差值是否超过第一阈值，如果是，则调整第一时钟信号的相位。

公开(公告)号：US08365119B2

公开(公告)日：2013-01-29

申请号：US12798971

申请日：2010-04-15

申请人： Stephen G. Tell

发明人： Stephen G. Tell

IPC分类号： G06F17/50

CPC分类号： G06F1/26 ,  G06F1/10 ,  G06F12/0246 ,  G06F13/382 ,  G06F13/4072 ,  G06F2212/7201 ,  G11C7/1072 ,  H03K19/1776 ,  H04L7/02

摘要： Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

公开(公告)号：US20100205343A1

公开(公告)日：2010-08-12

申请号：US12798971

申请日：2010-04-15

申请人： Stephen G. Tell

发明人： Stephen G. Tell

IPC分类号： G06F13/14

CPC分类号： G06F1/26 ,  G06F1/10 ,  G06F12/0246 ,  G06F13/382 ,  G06F13/4072 ,  G06F2212/7201 ,  G11C7/1072 ,  H03K19/1776 ,  H04L7/02

摘要： Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

公开(公告)号：US07735037B2

公开(公告)日：2010-06-08

申请号：US11321836

申请日：2005-12-29

申请人： Stephen G. Tell

发明人： Stephen G. Tell

IPC分类号： G06F17/50

CPC分类号： G06F1/26 ,  G06F1/10 ,  G06F12/0246 ,  G06F13/382 ,  G06F13/4072 ,  G06F2212/7201 ,  G11C7/1072 ,  H03K19/1776 ,  H04L7/02

摘要： Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

摘要翻译： 描述了一种用于控制在设备之间传输的信号的接口时序和/或电压操作的系统和方法。 处理器可以通过总线的一个或多个总线接口耦合到一个或多个对应的接口定时和/或电压比较电路以及对应的接口定时和/或电压调节电路。

公开(公告)号：US06556628B1

公开(公告)日：2003-04-29

申请号：US09302461

申请日：1999-04-29

申请人： John W. Poulton ,  Stephen G. Tell ,  Robert E. Palmer

发明人： John W. Poulton ,  Stephen G. Tell ,  Robert E. Palmer

IPC分类号： H04B300

CPC分类号： H04L25/4925 ,  H04L25/0266 ,  H04L25/085

摘要： Methods and systems for differential signaling include transmitting differential signals over N conductors, where N is greater than 2, from a sender to a receiver. The sender includes multiple transmitters that receive digital data and produce output signals based on the digital data. The output signals result in currents on conductors between the transmitters and multiple receivers. For any given symbol, the sum of the currents on the conductors is preferably equal to zero. In addition, a voltage difference preferably exists across the input terminals of each receiver. Methods and systems for coding binary data for transmission over a multi-conductor differential signaling system include converting input binary data into symbol numbers, converting the symbol numbers into valid drive words for a multi-conductor differential signaling system, and inputting the valid drive words to multiple differential transmitters.

摘要翻译： 用于差分信号的方法和系统包括从N个导体发送差分信号，其中N大于2，从发送器到接收器。 发送器包括接收数字数据并根据数字数据产生输出信号的多个发射器。 输出信号会导致发射器和多个接收器之间导体上的电流。 对于任何给定的符号，导体上的电流之和优选等于零。 此外，优选地，在每个接收器的输入端子之间存在电压差。 用于编码用于通过多导体差分信号系统传输的二进制数据的方法和系统包括将输入二进制数据转换成符号号，将符号数转换成用于多导体差分信号系统的有效驱动字，以及将有效驱动字输入到 多个差分发射机。

公开(公告)号：US07664166B2

公开(公告)日：2010-02-16

申请号：US11013945

申请日：2004-12-17

申请人： Robert E. Palmer ,  Thomas H. Greer, III ,  Stephen G. Tell

发明人： Robert E. Palmer ,  Thomas H. Greer, III ,  Stephen G. Tell

IPC分类号： H04B1/00

CPC分类号： H03L7/0812 ,  H04L7/0012 ,  H04L7/0025 ,  H04L7/005 ,  H04L7/0091

摘要： A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.

摘要翻译： 公开了一种同步中继器系统及其组件。 在一个特定的示例性实施例中，可以实现一个同步中继器系统组件作为接收器电路，该接收器电路包括将参考时钟信号乘以整数倍的时钟乘法器以产生数据时钟信号。 接收机电路还可以包括分频器电路，其产生具有不是参考时钟信号的频率的整数除数的频率的定时参考信号。