公开(公告)号：US20120161294A1

公开(公告)日：2012-06-28

申请号：US12978492

申请日：2010-12-24

申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/0802 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

摘要翻译： 在每个晶片被形成为包括暴露高精度电路的电路内部的可调节电路元件的开口的过程中，每个具有多个高精度电路和相应的微调控制电路的多个晶片被批量修整。 高精度电路和微调控制电路在修整阶段通过沿着锯木街道行进的金属轨迹进行电激活。 该方法将晶片接触结构连接到每个晶片以电激活金属迹线。 该方法将具有晶片接触结构的晶片放置在当高精度电路的实际输出电压与高精度电路的预测输出电压不匹配时，暴露的可调节电路元件被电镀或阳极化的解决方案中。

公开(公告)号：US20110260248A1

公开(公告)日：2011-10-27

申请号：US12768295

申请日：2010-04-27

申请人： Peter Smeys ,  Peter Johnson ,  Peter J. Hopper ,  William French

发明人： Peter Smeys ,  Peter Johnson ,  Peter J. Hopper ,  William French

IPC分类号： H01L29/786 ,  H01L21/768

CPC分类号： H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： A silicon-on-insulator (SOI) wafer is formed to have through-the-wafer contacts, and trench based interconnect structures on the back side of the SOI wafer that electrically connect the through-the-wafer contacts. In addition, selected ones of the through-the-wafer contacts bias the bodies of the MOS transistors.

摘要翻译： 形成绝缘体上硅（SOI）晶片以具有贯穿晶片的触点，以及SOI晶片的背侧上的沟槽基互连结构，其电连接晶片间的触点。 此外，通过晶片间接触的选定的一个偏压MOS晶体管的主体。

公开(公告)号：US08377792B2

公开(公告)日：2013-02-19

申请号：US12756097

申请日：2010-04-07

申请人： Peter J. Hopper ,  William French ,  Peter Smeys ,  Peter Johnson

发明人： Peter J. Hopper ,  William French ,  Peter Smeys ,  Peter Johnson

IPC分类号： H01L21/027 ,  H01L21/266

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.

摘要翻译： 具有大量板和微法拉范围内的电容的交叉指向的半导体电容器仅在单个光刻步骤上形成在晶片上，通过沉积与晶片间隔开的第一荫罩，每个奇数层的金属， 以及通过与晶片间隔开的第二荫罩的每个偶数金属层。

公开(公告)号：US08274129B2

公开(公告)日：2012-09-25

申请号：US12589491

申请日：2009-10-23

申请人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

发明人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

IPC分类号： H01L23/58

CPC分类号： H01L29/7835 ,  H01L21/76898 ,  H01L29/407 ,  H01L29/66659

摘要： A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.

摘要翻译： 一种方法包括在绝缘体上半导体结构的第一侧上形成晶体管器件。 绝缘体上半导体结构包括衬底，电介质层和衬底和电介质层之间的掩埋层。 该方法还包括通过绝缘体上半导体结构形成导电插塞。 导电插头与晶体管器件电连接。 该方法还包括在绝缘体上半导体结构的第二侧上形成场板，其中场板与导电插头电连接。 晶体管器件可以具有至少600V的击穿电压，并且场板可以沿着晶体管器件的长度的至少40％延伸。

公开(公告)号：US20110250730A1

公开(公告)日：2011-10-13

申请号：US12756097

申请日：2010-04-07

申请人： Peter J. Hopper ,  William French ,  Peter Smeys ,  Peter Johnson

发明人： Peter J. Hopper ,  William French ,  Peter Smeys ,  Peter Johnson

IPC分类号： H01L21/02

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.

摘要翻译： 具有大量板和微法拉范围内的电容的交叉指向的半导体电容器仅在单个光刻步骤上形成在晶片上，通过沉积与晶片间隔开的第一荫罩，每个奇数层的金属， 以及通过与晶片间隔开的第二荫罩的每个偶数金属层。

公开(公告)号：US08378460B2

公开(公告)日：2013-02-19

申请号：US12978492

申请日：2010-12-24

申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/0802 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

摘要翻译： 在每个晶片被形成为包括暴露高精度电路的电路内部的可调节电路元件的开口的过程中，每个具有多个高精度电路和相应的微调控制电路的多个晶片被批量修整。 高精度电路和微调控制电路在修整阶段通过沿着锯木街道行进的金属轨迹进行电激活。 该方法将晶片接触结构连接到每个晶片以电激活金属迹线。 该方法将具有晶片接触结构的晶片放置在当高精度电路的实际输出电压与高精度电路的预测输出电压不匹配时，暴露的可调节电路元件被电镀或阳极化的解决方案中。

公开(公告)号：US20110095365A1

公开(公告)日：2011-04-28

申请号：US12589491

申请日：2009-10-23

申请人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

发明人： William French ,  Peter Smeys ,  Peter J. Hopper ,  Peter Johnson

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L29/7835 ,  H01L21/76898 ,  H01L29/407 ,  H01L29/66659

摘要： A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device.

摘要翻译： 一种方法包括在绝缘体上半导体结构的第一侧上形成晶体管器件。 绝缘体上半导体结构包括衬底，电介质层和衬底和电介质层之间的掩埋层。 该方法还包括通过绝缘体上半导体结构形成导电插塞。 导电插头与晶体管器件电连接。 该方法还包括在绝缘体上半导体结构的第二侧上形成场板，其中场板与导电插头电连接。 晶体管器件可以具有至少600V的击穿电压，并且场板可以沿着晶体管器件的长度的至少40％延伸。

公开(公告)号：US20110272780A1

公开(公告)日：2011-11-10

申请号：US12774532

申请日：2010-05-05

申请人： Peter Smeys ,  Kyuwoon Hwang ,  Peter J. Hopper ,  William French

发明人： Peter Smeys ,  Kyuwoon Hwang ,  Peter J. Hopper ,  William French

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： An on-chip inductor structure is formed as part of an integrated circuit structure. The integrate circuit structure includes a semiconductor substrate having a top side and a back side, integrated circuit elements formed on the top side of the substrate, a conductive interconnect structure formed in contact with the integrated circuit elements and a passivation layer formed over the integrated circuit elements. The inductor structure comprises a layer of photoimageable epoxy formed on the passivation layer, a conductive inductor coil formed on the layer of photoimageable epoxy and at least one conductive via that extends from the inductor coil to the interconnect layer to provide electrical connection therebetween. Additionally, a back side trench may be formed in the back side of the semiconductor substrate beneath the inductor coil.

摘要翻译： 片上电感器结构形成为集成电路结构的一部分。 集成电路结构包括具有顶侧和背面的半导体衬底，形成在衬底的顶侧上的集成电路元件，与集成电路元件接触形成的导电互连结构和形成在集成电路上的钝化层 元素。 电感器结构包括形成在钝化层上的可光成像环氧树脂层，形成在可光成像环氧树脂层上的导电电感线圈和从电感线圈延伸到互连层的至少一个导电通孔，以在它们之间提供电连接。 此外，可以在电感线圈下方的半导体衬底的背面形成背面沟槽。

公开(公告)号：US08390093B1

公开(公告)日：2013-03-05

申请号：US13230171

申请日：2011-09-12

申请人： Peter J. Hopper ,  Peter Smeys ,  William French ,  Andrei Papou ,  Aditi Dutt Chaudhuri

发明人： Peter J. Hopper ,  Peter Smeys ,  William French ,  Andrei Papou ,  Aditi Dutt Chaudhuri

IPC分类号： H01L21/70 ,  H01L21/00 ,  H04B1/44

CPC分类号： H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.

摘要翻译： 电隔离系统通过使用半导体衬底的电导率调制在数字传输集成电路中提供电隔离。 衬底的导电性的调制影响了通过足够量的电介质材料与衬底隔离的（差分）RF电感器的涡电流损耗，这提供了通过隔离屏障从调制衬底到电感器的信号传递的基础 。

公开(公告)号：US20130062725A1

公开(公告)日：2013-03-14

申请号：US13230171

申请日：2011-09-12

申请人： Peter J. Hopper ,  Peter Smeys ,  William French ,  Andrei Papou ,  Chaudhuri Dutt Adilti

发明人： Peter J. Hopper ,  Peter Smeys ,  William French ,  Andrei Papou ,  Chaudhuri Dutt Adilti

IPC分类号： H01L29/02 ,  H01L21/02 ,  H01L21/31

CPC分类号： H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A galvanic isolation system provides galvanic isolation in digital transfer integrated circuits by using conductivity modulation of the semiconductor substrate. Modulation of the conductivity of the substrate affects eddy current losses of a (differential) RF inductor that is isolated from the substrate by a sufficient amount of dielectric material, which provides a basis for signal transfer from the modulated substrate to the inductor across the isolation barrier.

摘要翻译： 电隔离系统通过使用半导体衬底的电导率调制在数字传输集成电路中提供电隔离。 衬底的导电性的调制影响了通过足够量的电介质材料与衬底隔离的（差分）RF电感器的涡电流损耗，这提供了通过隔离屏障从调制衬底到电感器的信号传递的基础 。