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16 条记录 (耗时 0.022 秒)

    Method and system for providing electrical insulation for local interconnect in a logic circuit
    1.
    发明授权
    Method and system for providing electrical insulation for local interconnect in a logic circuit 有权
    在逻辑电路中为局部互连提供电绝缘的方法和系统

    公开(公告)号：US06303949B2

    公开(公告)日：2001-10-16

    申请号：US09262130

    申请日：1999-03-03

    申请人： William George En ,  Sunil Mehta ,  Fei Wang ,  Stewart Gordon Logie

    发明人： William George En ,  Sunil Mehta ,  Fei Wang ,  Stewart Gordon Logie

    IPC分类号： H01L2710

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.

    摘要翻译： 本发明提供了一种用于在逻辑电路中为局部互连提供电绝缘的方法和系统。 根据本发明的用于在制造逻辑电路期间为局部互连提供电气安装的系统和方法包括以下步骤：在半导体晶片上提供第一材料层，并在第一层上提供第二材料层。 另外，在逻辑电路的一部分上提供光电阻材料以进行电绝缘。 然后蚀刻由光致抗蚀剂材料未被保护的第一和第二层的部分。 然后在第一层和第二层上提供至少第三层，并且蚀刻第三层，使得第一层作为逻辑电路部分上的电绝缘。

    Method and system for providing electrical insulation for local interconnect in a logic circuit
    2.
    发明授权
    Method and system for providing electrical insulation for local interconnect in a logic circuit 失效
    在逻辑电路中为局部互连提供电绝缘的方法和系统

    公开(公告)号：US5956610A

    公开(公告)日：1999-09-21

    申请号：US861897

    申请日：1997-05-22

    申请人： William George En ,  Sunil Mehta ,  Fei Wang ,  Stewart Gordon Logie

    发明人： William George En ,  Sunil Mehta ,  Fei Wang ,  Stewart Gordon Logie

    IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： The present invention provides a method and system for providing electrical insulation for local interconnect in a logic circuit. A system and method according to the present invention for providing electrical installation for local interconnects during manufacturing of a logic circuit comprising the steps of providing a first layer of material over a semiconductor wafer and providing a second layer of material over the first layer. Additionally, a photoresist material is provided over a portion of the logic circuit to be electrically insulated. Portions of the first and second layers which are unprotected by the photoresist material are then etched. At least a third layer is then provided over the first and second layers, and the third layer is etched such that the first layer as an electrical insulation over the portion of the logic circuit.

    摘要翻译： 本发明提供了一种用于在逻辑电路中为局部互连提供电绝缘的方法和系统。 根据本发明的用于在制造逻辑电路期间为局部互连提供电气安装的系统和方法包括以下步骤：在半导体晶片上提供第一材料层，并在第一层上提供第二材料层。 另外，在逻辑电路的一部分上提供光电阻材料以进行电绝缘。 然后蚀刻由光致抗蚀剂材料未被保护的第一和第二层的部分。 然后在第一层和第二层上提供至少第三层，并且蚀刻第三层，使得第一层作为逻辑电路部分上的电绝缘。

    Shallow junction semiconductor
    3.
    发明授权
    Shallow junction semiconductor 失效
    浅结半导体

    公开(公告)号：US07298012B2

    公开(公告)日：2007-11-20

    申请号：US11307537

    申请日：2006-02-11

    申请人： Mario M. Pelella ,  William George En ,  Eric Paton ,  Witold P. Maszara

    发明人： Mario M. Pelella ,  William George En ,  Eric Paton ,  Witold P. Maszara

    IPC分类号： H01L29/76

    CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

    摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.

    摘要翻译： 提供了具有半导体衬底的集成电路。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 硅化物层位于与栅极和栅极电介质相邻的半导体衬底上。 硅化物层在其中包含基本均匀分布和浓缩的掺杂剂。 浅层源极/漏极结在自对准层下面。 层间电介质位于半导体衬底之上，并且触点位于硅化物层的层间电介质中。

    Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby
    4.
    发明授权
    Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby 有权
    由此产生的半导体固相外延损伤控制方法和集成电路

    公开(公告)号：US06933579B1

    公开(公告)日：2005-08-23

    申请号：US10728001

    申请日：2003-12-03

    申请人： William George En ,  Witold P. Maszara ,  Mario M. Pelella

    发明人： William George En ,  Witold P. Maszara ,  Mario M. Pelella

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/66628 ,  H01L21/26506 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A raised source/drain layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. An amorphized shallow source/drain extension implanted region is formed in the raised source/drain layer and the semiconductor substrate therebeneath. The amorphized region is then recrystallized to form a shallow source/drain extension having residual recrystallization damage elevated into the raised source/drain layer.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 凸起的源极/漏极层形成在与栅极和栅极电介质相邻的半导体衬底上。 在凸起的源极/漏极层和其下的半导体衬底上形成非晶化的浅源极/漏极延伸注入区。 然后将非晶化区域重结晶以形成具有升高到升高的源极/漏极层中的残余再结晶损伤的浅源/漏极延伸。

    Self-aligned floating body control for SOI device through leakage enhanced buried oxide
    5.
    发明授权
    Self-aligned floating body control for SOI device through leakage enhanced buried oxide 有权
    用于SOI器件的自对准浮体控制通过泄漏增强掩埋氧化物

    公开(公告)号：US06509613B1

    公开(公告)日：2003-01-21

    申请号：US09849494

    申请日：2001-05-04

    申请人： William George En ,  Srinath Krishnan ,  Judy Xilin An

    发明人： William George En ,  Srinath Krishnan ,  Judy Xilin An

    IPC分类号： H01L2701

    CPC分类号： H01L29/66772 ,  H01L29/78612

    摘要： A semiconductor-on-insulator (SOI) device formed on an SOI structure with a buried oxide (BOX) layer disposed therein and an active region disposed on the BOX layer having active regions defined by isolation trenches and the BOX layer. The SOI device includes a gate formed over one of the active regions. The gate defines a channel interposed between a source and a drain formed within one of the active regions. The SOI device includes a leakage enhanced region within the BOX layer defined by the gate.

    摘要翻译： 在SOI结构上形成有埋置氧化物（BOX）层的绝缘体上半导体器件（SOI）器件，以及设置在BOX层上的有源区域，其中有源区域由隔离沟槽和BOX层限定。 SOI器件包括形成在一个有源区上的栅极。 栅极限定插入在一个有源区域内形成的源极和漏极之间的沟道。 SOI器件包括由栅极限定的BOX层内的泄漏增强区域。

    Dual purpose test structure for gate-body current measurement in PD/SOI and for direct extraction of physical gate length in scaled CMOS technologies
    7.
    发明授权
    Dual purpose test structure for gate-body current measurement in PD/SOI and for direct extraction of physical gate length in scaled CMOS technologies 失效
    用于PD / SOI中门体电流测量的双重目的测试结构，以及在缩放CMOS技术中直接提取物理栅极长度

    公开(公告)号：US07132683B1

    公开(公告)日：2006-11-07

    申请号：US10838230

    申请日：2004-05-05

    申请人： Srinath Krishnan ,  William George En

    发明人： Srinath Krishnan ,  William George En

    IPC分类号： H01L23/58

    CPC分类号： H01L22/34 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure, for testing relative to an MOS transistor, closely resembles the MOS transistor of interest. For example, certain dimensions and a number of dopant concentrations typically are substantially the same in the test structure as found in corresponding elements of the MOS transistor of interest. However, the regions of the test structure corresponding to the source and drain of the transistor have no halos or extensions that might cause gate overlap; and in the test structure, these regions are of a semiconductor type opposite the type found in the source and drain of the transistor. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for direct electrical measurement of gate length.

    摘要翻译： 用于相对于MOS晶体管测试的结构非常类似于感兴趣的MOS晶体管。 例如，在感兴趣的MOS晶体管的相应元件中发现的测试结构中，某些尺寸和多个掺杂剂浓度通常基本相同。 然而，对应于晶体管的源极和漏极的测试结构的区域没有可能引起栅极重叠的光晕或延伸; 并且在测试结构中，这些区域是与在晶体管的源极和漏极中发现的类型相反的半导体类型。 该测试结构能够精确测量门体电流，用于建模浮体效应和/或用于栅极长度的直接电气测量。

    Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS
    8.
    发明授权
    Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS 失效
    使用常规CMOS制作门体电流测试结构并直接提取物理栅极长度的方法

    公开(公告)号：US07071044B1

    公开(公告)日：2006-07-04

    申请号：US10838229

    申请日：2004-05-05

    申请人： Srinath Krishnan ,  William George En

    发明人： Srinath Krishnan ,  William George En

    IPC分类号： H01L21/336

    CPC分类号： H01L21/84 ,  H01L22/34 ,  H01L29/105 ,  H01L29/78621

    摘要： A structure for testing relative to an MOS transistor, can be easily constructed as part of the CMOS process flow. A doped device well is formed, for example, in a silicon-on-insulator structure. The concentration level in the well corresponds to that for a well of the transistor. Gate insulator and polysilicon layers are formed, and the polysilicon is implanted with dopant, to a concentration level expected in the transistor gate. After gate patterning, the methodology involves forming sidewall spacers and implanting dopant into the active device well, to form regions in the test structure corresponding to the transistor source and drain. Although the concentrations mimic those in the transistor source and drain, these test structure regions are doped with opposite type dopant material. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for measurement of gate length.

    摘要翻译： 用于相对于MOS晶体管测试的结构可以容易地构建为CMOS工艺流程的一部分。 掺杂器件阱例如在绝缘体上硅结构中形成。 阱中的浓度水平对应于晶体管的阱。 形成栅极绝缘体和多晶硅层，并且将掺杂剂注入多晶硅至晶体管栅极中预期的浓度水平。 在栅极图案化之后，该方法涉及形成侧壁间隔物并将掺杂剂注入到有源器件阱中，以在对应于晶体管源极和漏极的测试结构中形成区域。 尽管浓度模拟晶体管源极和漏极中的浓度，但是这些测试结构区域掺杂有相反类型的掺杂剂材料。 测试结构能够准确测量门体电流，用于建模浮体效应和/或测量栅极长度。

    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
    9.
    发明授权
    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
    具有高K电介质的半导体器件具有渐变介电常数的间隔物

    公开(公告)号：US06764966B1

    公开(公告)日：2004-07-20

    申请号：US10085278

    申请日：2002-02-27

    申请人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

    发明人： William George En ,  Arvind Halliyal ,  Ming-Ren Lin ,  Minh Van Ngo ,  Chih-Yuh Yang

    IPC分类号： H01L2128

    CPC分类号： H01L29/6656 ,  H01L29/66833 ,  H01L29/78

    摘要： A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

    摘要翻译： 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括插入在栅电极和半导体衬底之间的电介质层。 此外，半导体器件包括形成在电介质层的侧壁，栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。 梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。