利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

42 条记录 (耗时 0.025 秒)

    Shallow junction semiconductor and method for the fabrication thereof
    1.
    发明授权
    Shallow junction semiconductor and method for the fabrication thereof 失效
    浅结半导体及其制造方法

    公开(公告)号：US07033916B1

    公开(公告)日：2006-04-25

    申请号：US10770990

    申请日：2004-02-02

    申请人： Mario M. Pelella ,  William George En ,  Eric Paton ,  Witold P. Maszara

    发明人： Mario M. Pelella ,  William George En ,  Eric Paton ,  Witold P. Maszara

    IPC分类号： H01L21/22 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/44

    CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A super-saturated doped source silicide metallic layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide metallic layer incorporates a substantially uniformly distributed dopant therein in a substantially uniform super-saturated concentration. The silicide metallic layer is reacted with the semiconductor substrate therebeneath to form a salicide layer and outdiffuse the dopant from the salicide layer into the semiconductor substrate therebeneath. The outdiffused dopant in the semiconductor substrate is then activated to form a shallow source/drain junction beneath the salicide layer. An interlayer dielectric is then deposited above the semiconductor substrate, and contacts are formed in the interlayer dielectric to the salicide layer.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在与栅极和栅极电介质相邻的半导体衬底上形成超饱和掺杂源极化硅金属层。 硅化金属层以基本均匀的超饱和浓度掺入其中基本上均匀分布的掺杂剂。 硅化物金属层与其下面的半导体衬底反应以形成自对准硅化物层，并将掺杂剂从硅化物层扩散到其内的半导体衬底中。 然后激活半导体衬底中的向外扩散的掺杂​​剂以在自对准硅化物层下面形成浅的源极/漏极结。 然后在半导体衬底上沉积层间电介质，并且在层间电介质中形成接触到硅化物层。

    Shallow junction semiconductor
    3.
    发明授权
    Shallow junction semiconductor 失效
    浅结半导体

    公开(公告)号：US07298012B2

    公开(公告)日：2007-11-20

    申请号：US11307537

    申请日：2006-02-11

    申请人： Mario M. Pelella ,  William George En ,  Eric Paton ,  Witold P. Maszara

    发明人： Mario M. Pelella ,  William George En ,  Eric Paton ,  Witold P. Maszara

    IPC分类号： H01L29/76

    CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

    摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.

    摘要翻译： 提供了具有半导体衬底的集成电路。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 硅化物层位于与栅极和栅极电介质相邻的半导体衬底上。 硅化物层在其中包含基本均匀分布和浓缩的掺杂剂。 浅层源极/漏极结在自对准层下面。 层间电介质位于半导体衬底之上，并且触点位于硅化物层的层间电介质中。

    Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby
    4.
    发明授权
    Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby 有权
    由此产生的半导体固相外延损伤控制方法和集成电路

    公开(公告)号：US06933579B1

    公开(公告)日：2005-08-23

    申请号：US10728001

    申请日：2003-12-03

    申请人： William George En ,  Witold P. Maszara ,  Mario M. Pelella

    发明人： William George En ,  Witold P. Maszara ,  Mario M. Pelella

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/66628 ,  H01L21/26506 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

    摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A raised source/drain layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. An amorphized shallow source/drain extension implanted region is formed in the raised source/drain layer and the semiconductor substrate therebeneath. The amorphized region is then recrystallized to form a shallow source/drain extension having residual recrystallization damage elevated into the raised source/drain layer.

    摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 凸起的源极/漏极层形成在与栅极和栅极电介质相邻的半导体衬底上。 在凸起的源极/漏极层和其下的半导体衬底上形成非晶化的浅源极/漏极延伸注入区。 然后将非晶化区域重结晶以形成具有升高到升高的源极/漏极层中的残余再结晶损伤的浅源/漏极延伸。

    METHODS OF FORMING DIFFERENT FINFET DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND INTEGRATED CIRCUIT PRODUCTS CONTAINING SUCH DEVICES
    5.
    发明申请
    METHODS OF FORMING DIFFERENT FINFET DEVICES WITH DIFFERENT THRESHOLD VOLTAGES AND INTEGRATED CIRCUIT PRODUCTS CONTAINING SUCH DEVICES 有权
    形成具有不同阈值电压的不同FINFET器件的方法和包含这些器件的集成电路产品

    公开(公告)号：US20140070322A1

    公开(公告)日：2014-03-13

    申请号：US13613508

    申请日：2012-09-13

    申请人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

    发明人： Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

    IPC分类号： H01L21/20 ,  H01L27/088

    CPC分类号： H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

    摘要： One illustrative method disclosed herein involves forming a first fin for a first FinFET device in and above a semiconducting substrate, wherein the first fin is comprised of a first semiconductor material that is different from the material of the semiconducting substrate and, after forming the first fin, forming a second fin for a second FinFET device that is formed in and above the semiconducting substrate, wherein the second fin is comprised of a second semiconductor material that is different from the material of the semiconducting substrate and different from the first semiconductor material.

    摘要翻译： 本文公开的一种说明性方法包括在半导体衬底中和上方形成用于第一FinFET器件的第一鳍片，其中第一鳍片由不同于半导体衬底的材料的第一半导体材料组成，并且在形成第一鳍片之后 形成在所述半导体衬底中以及所述半导体衬底上形成的第二FinFET器件的第二鳍片，其中所述第二鳍片由不同于所述半导体衬底的材料并且不同于所述第一半导体材料的第二半导体材料构成。

    METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS
    6.
    发明申请
    METHODS OF FORMING FINFET DEVICES WITH ALTERNATIVE CHANNEL MATERIALS 有权
    用替代通道材料形成FINFET器件的方法

    公开(公告)号：US20140011341A1

    公开(公告)日：2014-01-09

    申请号：US13544259

    申请日：2012-07-09

    申请人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. Licausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

    发明人： Witold P. Maszara ,  Ajey P. Jacob ,  Nicholas V. Licausi ,  Jody A. Fronheiser ,  Kerem Akarvardar

    IPC分类号： H01L21/20

    CPC分类号： H01L29/1054 ,  H01L29/66795 ,  H01L29/785

    摘要： One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

    摘要翻译： 一种方法包括提供由第一和第二半导体材料构成的衬底，通过硬掩模层执行蚀刻工艺以限定限定用于FinFET器件的鳍片的第一和第二部分的多个沟槽，其中第一部分是第一部分 并且第二部分是第二材料，在沟槽中形成绝缘材料层，对绝缘材料进行平面化处理，执行蚀刻工艺以去除硬掩模层并减小第二部分的厚度，由此限定 空腔，执行沉积工艺以在第二部分上形成翅片的第三部分，其中第三部分是不同于第二材料的第三半导体材料，并且执行一种工艺，使得蚀刻后的上表面 绝缘材料在第三部分的上表面下方。