Shallow junction semiconductor and method for the fabrication thereof
    1.
    发明授权
    Shallow junction semiconductor and method for the fabrication thereof 失效
    浅结半导体及其制造方法

    公开(公告)号:US07033916B1

    公开(公告)日:2006-04-25

    申请号:US10770990

    申请日:2004-02-02

    摘要: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A super-saturated doped source silicide metallic layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide metallic layer incorporates a substantially uniformly distributed dopant therein in a substantially uniform super-saturated concentration. The silicide metallic layer is reacted with the semiconductor substrate therebeneath to form a salicide layer and outdiffuse the dopant from the salicide layer into the semiconductor substrate therebeneath. The outdiffused dopant in the semiconductor substrate is then activated to form a shallow source/drain junction beneath the salicide layer. An interlayer dielectric is then deposited above the semiconductor substrate, and contacts are formed in the interlayer dielectric to the salicide layer.

    摘要翻译: 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质,在栅极电介质上形成栅极。 在与栅极和栅极电介质相邻的半导体衬底上形成超饱和掺杂源极化硅金属层。 硅化金属层以基本均匀的超饱和浓度掺入其中基本上均匀分布的掺杂剂。 硅化物金属层与其下面的半导体衬底反应以形成自对准硅化物层,并将掺杂剂从硅化物层扩散到其内的半导体衬底中。 然后激活半导体衬底中的向外扩散的掺杂​​剂以在自对准硅化物层下面形成浅的源极/漏极结。 然后在半导体衬底上沉积层间电介质,并且在层间电介质中形成接触到硅化物层。

    Shallow junction semiconductor
    3.
    发明授权
    Shallow junction semiconductor 失效
    浅结半导体

    公开(公告)号:US07298012B2

    公开(公告)日:2007-11-20

    申请号:US11307537

    申请日:2006-02-11

    IPC分类号: H01L29/76

    摘要: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.

    摘要翻译: 提供了具有半导体衬底的集成电路。 栅极电介质位于半导体衬底上,栅极位于栅极电介质上。 硅化物层位于与栅极和栅极电介质相邻的半导体衬底上。 硅化物层在其中包含基本均匀分布和浓缩的掺杂剂。 浅层源极/漏极结在自对准层下面。 层间电介质位于半导体衬底之上,并且触点位于硅化物层的层间电介质中。

    Zero interface polysilicon to polysilicon gate for flash memory
    4.
    发明授权
    Zero interface polysilicon to polysilicon gate for flash memory 有权
    零接口多晶硅到多晶硅栅极用于闪存

    公开(公告)号:US07863175B2

    公开(公告)日:2011-01-04

    申请号:US11614801

    申请日:2006-12-21

    IPC分类号: H01L21/8247 H01L29/788

    摘要: A system and method are disclosed for processing a zero angstrom oxide interface dual poly gate structure for a flash memory device. An exemplary method can include removing an oxide on a surface of a first poly layer and forming a second poly layer on the first poly layer in a same processing chamber. A transfer of the structure is not needed from an oxide removal tool to, for example, a poly layer formation tool, an implant tool, and the like. As a result, impurities containing a silicon oxide caused by exposure of the first poly layer to an oxygen-containing atmosphere do not form at the interface of the first and second poly layers.

    摘要翻译: 公开了一种用于处理闪存器件的零氧化物界面双重多晶硅结构的系统和方法。 示例性的方法可以包括去除第一多晶硅层的表面上的氧化物并在同一处理室中在第一多晶硅层上形成第二多晶硅层。 不需要从氧化物去除工具到例如多层形成工具,植入工具等的结构的转移。 结果,在第一和第二多层的界面处不形成含有由第一多晶硅层暴露于含氧气氛的氧化硅的杂质。

    SHALLOW JUNCTION SEMICONDUCTOR
    5.
    发明申请

    公开(公告)号:US20060180873A1

    公开(公告)日:2006-08-17

    申请号:US11307537

    申请日:2006-02-11

    摘要: An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A suicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.

    摘要翻译: 提供了具有半导体衬底的集成电路。 栅极电介质位于半导体衬底上,栅极位于栅极电介质上。 硅化物层位于邻近栅极和栅极电介质的半导体衬底上。 硅化物层在其中包含基本均匀分布和浓缩的掺杂剂。 浅层源极/漏极结在自对准层下面。 层间电介质位于半导体衬底之上,并且触点位于硅化物层的层间电介质中。

    Method of eliminating voids in W plugs
    7.
    发明授权
    Method of eliminating voids in W plugs 失效
    消除W插头空隙的方法

    公开(公告)号:US06638861B1

    公开(公告)日:2003-10-28

    申请号:US09986263

    申请日:2001-11-08

    IPC分类号: H01L2144

    CPC分类号: C25D5/50 H01L21/76882

    摘要: Reliable contacts/vias are formed by filling an opening in a dielectric layer with W and laser thermal annealing to eliminate or significantly reduce voids. Embodiments include depositing W to fill a contact/via opening in an interlayer dielectric, laser thermal annealing in N2 to elevate the temperature of the W filling the contact/via opening and reflow the W thereby eliminating voids. Embodiments include conducting CMP either before or subsequent to laser thermal annealing.

    摘要翻译: 通过用W和激光热退火填充介电层中的开口来形成可靠的触点/通孔,以消除或显着减少空隙。 实施例包括沉积W以填充层间电介质中的接触/通孔开口,在N2中进行激光热退火以升高填充接触/通孔开口的W的温度并回流W,从而消除空隙。 实施例包括在激光热退火之前或之后进行CMP。

    Method of forming reliable Cu interconnects
    8.
    发明授权
    Method of forming reliable Cu interconnects 失效
    形成可靠的Cu互连的方法

    公开(公告)号:US06727176B2

    公开(公告)日:2004-04-27

    申请号:US09986267

    申请日:2001-11-08

    IPC分类号: H01L2144

    CPC分类号: H01L21/76882

    摘要: Reliable Cu interconnects are formed by filling an opening in a dielectric layer with Cu and then laser thermal annealing in NH3 to reduce copper oxide and to reflow the deposited Cu, thereby eliminating voids and reducing contact resistance. Embodiments include laser thermal annealing employing an NH3 flow rate of about 200 to about 2,000 sccn.

    摘要翻译: 通过用Cu填充电介质层中的开口,然后在NH 3中激光热退火以形成可靠的Cu互连,以减少氧化铜和回流沉积的Cu,从而消除空隙并降低接触电阻。 实施例包括使用约200至约2,000sccn的NH 3流速的激光热退火。

    Method of salicide formation
    9.
    发明授权
    Method of salicide formation 失效
    自杀剂形成方法

    公开(公告)号:US06399467B1

    公开(公告)日:2002-06-04

    申请号:US09733779

    申请日:2000-12-08

    IPC分类号: H01L213205

    摘要: A method of forming a self-aligned silicide (salicide) with a screening oxide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area which is advantageously about two to three times thicker than silicide formations over the source and drain areas.

    摘要翻译: 用筛选氧化物形成自对准硅化物(自对准硅化物)的方法。 该方法通过降低源极和漏极区域中的漏电流并降低栅极的多晶硅片电阻来提高晶体管的速度。 作为本方法的一个实施例的结果,在栅极区域上形成硅化物,其优选在源极和漏极区域上比硅化物层厚约2至3倍。

    Method of salicide formation by siliciding a gate area prior to siliciding a source and drain area
    10.
    发明授权
    Method of salicide formation by siliciding a gate area prior to siliciding a source and drain area 有权
    在将源极和漏极区域硅化之前通过硅化栅极区域形成硅化物的方法

    公开(公告)号:US06387786B1

    公开(公告)日:2002-05-14

    申请号:US09733778

    申请日:2000-12-08

    IPC分类号: H01L21285

    CPC分类号: H01L29/66507 H01L29/4933

    摘要: The present invention relates to a method of forming a self-aligned silicide (salicide) by siliciding a gate area prior to siliciding a source and drain area and/or spacer formation. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area that is advantageously thicker than silicide formations over the source and drain areas.

    摘要翻译: 本发明涉及通过在将源极和漏极区域和/或间隔物形成硅化之前将栅极区域硅化来形成自对准硅化物(自对准硅化物)的方法。 该方法通过降低源极和漏极区域中的漏电流并降低栅极的多晶硅片电阻来提高晶体管的速度。 作为本方法的一个实施例的结果,在栅极区域上形成硅化物,其优选在源极和漏极区域上比硅化物层更厚。