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    Two-level scheduler for multi-threaded processing
    1.
    发明授权
    Two-level scheduler for multi-threaded processing 有权
    用于多线程处理的两级调度器

    公开(公告)号：US08732711B2

    公开(公告)日：2014-05-20

    申请号：US13151094

    申请日：2011-06-01

    申请人： William James Dally ,  Stephen William Keckler ,  David Tarjan ,  John Erik Lindholm ,  Mark Alan Gebhart ,  Daniel Robert Johnson

    发明人： William James Dally ,  Stephen William Keckler ,  David Tarjan ,  John Erik Lindholm ,  Mark Alan Gebhart ,  Daniel Robert Johnson

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3887

    摘要： One embodiment of the present invention sets forth a technique for scheduling thread execution in a multi-threaded processing environment. A two-level scheduler maintains a small set of active threads called strands to hide function unit pipeline latency and local memory access latency. The strands are a sub-set of a larger set of pending threads that is also maintained by the two-leveler scheduler. Pending threads are promoted to strands and strands are demoted to pending threads based on latency characteristics. The two-level scheduler selects strands for execution based on strand state. The longer latency of the pending threads is hidden by selecting strands for execution. When the latency for a pending thread is expired, the pending thread may be promoted to a strand and begin (or resume) execution. When a strand encounters a latency event, the strand may be demoted to a pending thread while the latency is incurred.

    摘要翻译： 本发明的一个实施例提出了一种用于在多线程处理环境中调度线程执行的技术。 一个两级调度程序维护一组称为线索的活动线程，以隐藏功能单元流水线延迟和本地存储器访问延迟。 这些链是一组更大的待处理线程的子集，其也由二级调度器维护。 等待线程被提升为线索，并且基于延迟特性将线降级到等待线程。 两级调度器基于线状态来选择用于执行的线。 通过选择要执行的链来隐藏待处理线程的延迟更长。 当待处理线程的等待时间到期时，挂起的线程可以被提升为一个线并开始（或恢复）执行。 当一条线遇到一个延迟事件时，该链可以被降级到等待线程，同时发生延迟。

    Unified streaming multiprocessor memory
    4.
    发明授权
    Unified streaming multiprocessor memory 有权
    统一流式多处理器内存

    公开(公告)号：US09069664B2

    公开(公告)日：2015-06-30

    申请号：US13240366

    申请日：2011-09-22

    申请人： William James Dally

    发明人： William James Dally

    IPC分类号： G06F13/00 ,  G06F12/06 ,  G06F13/16

    CPC分类号： G06F12/06 ,  G06F13/16 ,  G06F13/1605 ,  G06F2213/0038

    摘要： One embodiment of the present invention sets forth a technique for providing a unified memory for access by execution threads in a processing system. Several logically separate memories are combined into a single unified memory that includes a single set of shared memory banks, an allocation of space in each bank across the logical memories, a mapping rule that maps the address space of each logical memory to its partition of the shared physical memory, a circuitry including switches and multiplexers that supports the mapping, and an arbitration scheme that allocates access to the banks.

    摘要翻译： 本发明的一个实施例提出了一种用于在处理系统中提供用于由执行线程访问的统一存储器的技术。 几个逻辑上分离的存储器被组合成单个统一存储器，其包括单个共享存储器组集合，跨越逻辑存储器的每个存储体中的空间分配;将每个逻辑存储器的地址空间映射到其分区的映射规则 共享物理存储器，包括支持映射的交换机和多路复用器的电路以及分配对存储体的访问的仲裁方案。

    Hierarchical memory addressing
    5.
    发明授权
    Hierarchical memory addressing 有权
    分层存储器寻址

    公开(公告)号：US08982140B2

    公开(公告)日：2015-03-17

    申请号：US13241745

    申请日：2011-09-23

    申请人： William James Dally

    发明人： William James Dally

    IPC分类号： G06F13/28 ,  G06F15/16 ,  G06F12/02 ,  G06F12/08

    CPC分类号： G06F12/0284 ,  G06F12/08 ,  G06F12/0811 ,  G06F2212/251 ,  G06F2212/2515 ,  G06F2212/253 ,  G06F2212/302 ,  G06F2213/0038

    摘要： One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

    摘要翻译： 本发明的一个实施例提出了一种用于在分层图形处理单元簇中寻址数据的技术。 基于目标数据单元所在的存储电路的位置构建分层地址。 分层地址包括指示数据单元的层次级别的级别字段和指示GPU簇内的GPU当前存储数据单元的节点标识符。 分层地址还可以包括一个或多个标识符，其指示特定层级中的哪个存储电路当前存储数据单元。 层次结构地址是基于层次域构建和解释的。 该技术有利地使得在GPU集群内执行的程序能够使用分层地址高效地访问驻留在其它GPU中的数据。

    Hierarchical Memory Addressing
    6.
    发明申请
    Hierarchical Memory Addressing 有权
    分层内存寻址

    公开(公告)号：US20120075319A1

    公开(公告)日：2012-03-29

    申请号：US13241745

    申请日：2011-09-23

    申请人： William James Dally

    发明人： William James Dally

    IPC分类号： G06F13/00 ,  G06F12/06

    CPC分类号： G06F12/0284 ,  G06F12/08 ,  G06F12/0811 ,  G06F2212/251 ,  G06F2212/2515 ,  G06F2212/253 ,  G06F2212/302 ,  G06F2213/0038

    摘要： One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

    摘要翻译： 本发明的一个实施例提出了一种用于在分层图形处理单元簇中寻址数据的技术。 基于目标数据单元所在的存储电路的位置构建分层地址。 分层地址包括指示数据单元的层次级别的级别字段和指示GPU簇内的GPU当前存储数据单元的节点标识符。 分层地址还可以包括一个或多个标识符，其指示特定层级中的哪个存储电路当前存储数据单元。 层次结构地址是基于层次域构建和解释的。 该技术有利地使得在GPU集群内执行的程序能够使用分层地址高效地访问驻留在其它GPU中的数据。

    Latch circuit with a bridging device
    7.
    发明授权
    Latch circuit with a bridging device 有权
    带桥接器的锁存电路

    公开(公告)号：US08659337B2

    公开(公告)日：2014-02-25

    申请号：US13188364

    申请日：2011-07-21

    申请人： Ilyas Elkin ,  William James Dally ,  Jonah M. Alben

    发明人： Ilyas Elkin ,  William James Dally ,  Jonah M. Alben

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356 ,  H03K3/356026 ,  H03K3/356052 ,  H03K3/356147 ,  H03K3/356191

    摘要： One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

    摘要翻译： 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。

    Power supply-insensitive buffer and oscillator circuit
    8.
    发明授权
    Power supply-insensitive buffer and oscillator circuit 有权
    电源不敏感缓冲器和振荡器电路

    公开(公告)号：US08604857B2

    公开(公告)日：2013-12-10

    申请号：US13294025

    申请日：2011-11-10

    申请人： William James Dally

    发明人： William James Dally

    IPC分类号： H03H11/26

    CPC分类号： H03H11/265

    摘要： One embodiment of the present invention sets forth a technique for reducing jitter caused by changes in a power supply for a clock generated by a ring oscillator of inverter devices. An inverter sub-circuit is coupled in parallel with a current-starved inverter sub-circuit to produce an inverter circuit that is insensitive to changes in the power supply voltage. When the ring oscillator is used as the voltage controlled oscillator of a phase locked loop, the delay of the inverters may be controlled by varying a bias current for each inverter in response to changes in the power supply voltage to reduce any jitter in a clock output produced by the changes in the power supply voltage. When the transistor devices are sized appropriately and the bias current is adjusted, the sensitivity of the inverter circuit to changes in the power supply voltage may be reduced.

    摘要翻译： 本发明的一个实施例提出了一种用于减少由逆变器装置的环形振荡器产生的时钟的电源的变化引起的抖动的技术。 逆变器子电路与电流欠压逆变器子电路并联耦合，以产生对电源电压变化不敏感的逆变器电路。 当环形振荡器用作锁相环的压控振荡器时，可以通过响应于电源电压的变化改变每个逆变器的偏置电流来控制反相器的延迟，以减少时钟输出中的任何抖动 由电源电压的变化产生。 当晶体管器件的尺寸适当并且调节偏置电流时，可以减小逆变器电路对电源电压变化的灵敏度。

    Data exchange and communication between execution units in a parallel processor
    9.
    发明授权
    Data exchange and communication between execution units in a parallel processor 有权
    并行处理器中执行单元之间的数据交换和通信

    公开(公告)号：US08024553B2

    公开(公告)日：2011-09-20

    申请号：US12192813

    申请日：2008-08-15

    申请人： Brucek Khailany ,  William James Dally ,  Ujval J. Kapasi ,  Jim Jian Lin

    发明人： Brucek Khailany ,  William James Dally ,  Ujval J. Kapasi ,  Jim Jian Lin

    IPC分类号： G06F9/44 ,  G06F15/76

    CPC分类号： G06F9/30014 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3891

    摘要： A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.

    摘要翻译： 一种具有多个执行通道的集成电路处理装置内的操作方法。 在接收到在执行通道之间交换数据的指令时，检查来自执行通道的相应请求，以确定在第一间隔期间可以将数据发送到执行通道的一个或多个其他执行通道的集合。 用信号通知执行通道集合内的每个执行通道，以指示执行通道可以向执行通道中的一个或其他执行通道发送数据。

    System and method for explicitly managing cache coherence
    10.
    发明授权
    System and method for explicitly managing cache coherence 有权
    明确管理缓存一致性的系统和方法

    公开(公告)号：US08788761B2

    公开(公告)日：2014-07-22

    申请号：US13243948

    申请日：2011-09-23

    申请人： William James Dally

    发明人： William James Dally

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0817 ,  G06F12/0842

    摘要： One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed.

    摘要翻译： 本发明的一个实施例阐述了对具有两个显式控制状态P（私有）和R（只读））的高速缓存一致性协议的扩展，其提供对程序逻辑可以保证正确的高速缓存行的显式程序控制 行为。 在私有状态下，只有高速缓存行的所有者可以访问高速缓存行进行读取或写入操作。 在只读状态下，只能对高速缓存线执行读操作，从而不允许执行写操作。