-
公开(公告)号：US5557755A
公开(公告)日：1996-09-17
申请号：US201461
申请日：1994-02-24
CPC分类号： G06F13/4022
摘要： In a bus system including a bus, a plurality of nodes including a primary node, and a bus access coordinator, bus utilization efficiency is improved by operating the coordinator at the same clock frequency as the primary node. The primary node is the node in the bus system which accesses the bus most frequently. By running the coordinator synchronous with the primary node, the need for synchronization events between the two components is eliminated. Since the primary node accesses the bus most frequently, eliminating synchronization events with the primary node eliminates most of the synchronization events in the bus system. Thus, synchronization events are minimized which, in turn, improves bus utilization efficiency.
摘要翻译： 在包括总线，包括主节点的多个节点和总线访问协调器的总线系统中，通过以与主节点相同的时钟频率操作协调器来提高总线利用效率。 主节点是总线系统中最频繁访问总线的节点。 通过运行与主节点同步的协调器，消除了两个组件之间的同步事件的需要。 由于主节点最频繁地访问总线，消除与主节点的同步事件消除了总线系统中的大部分同步事件。 因此，同步事件被最小化，这又提高总线利用效率。
-
公开(公告)号：US5630077A
公开(公告)日：1997-05-13
申请号：US626905
申请日：1996-04-04
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： To optimize system bus utilization in a computer system, a bus coordinator is included in the computer system to coordinate the transfer of information signals on the bus. Each time a source node wishes to transfer information to a destination node, the source node sends a request to the coordinator along with the identification of the destination node. Upon receiving this request, the coordinator determines whether the destination node has capacity to receive information signals. If the destination node has capacity, then the coordinator grants control of the system bus to the source node to allow the source node to send information signals to the destination node via the system bus. Otherwise, the source node is denied control of the system bus until the destination node has capacity to receive information signals. By granting control of the system bus to a source node only when the destination node has capacity to receive information signals, the coordinator ensures that no system bus time is wasted on unsuccessful information transfers. Thus, bus utilization is optimized.
摘要翻译： 为了优化计算机系统中的系统总线利用率，计算机系统中包括总线协调器，以协调总线上信息信号的传输。 每当源节点希望将信息传送到目的地节点时，源节点与目的地节点的标识一起向协调器发送请求。 在接收到该请求之后，协调器确定目的地节点是否具有接收信息信号的能力。 如果目标节点具有容量，则协调器将系统总线的控制权授予源节点，以允许源节点通过系统总线向目的地节点发送信息信号。 否则，源节点被拒绝对系统总线的控制，直到目的节点具有接收信息信号的能力。 只有当目的地节点具有接收信息信号的能力时，通过将系统总线的控制权授予源节点，协调器才能确保不会在不成功的信息传输上浪费系统总线时间。 因此，优化了总线利用率。
-
3.发明授权
公开(公告)号：US5590130A
公开(公告)日：1996-12-31
申请号：US510557
申请日：1995-08-02
IPC分类号： G06F13/364 , G06F13/42 , H04L12/417
CPC分类号： G06F13/364 , G06F13/4217
摘要： A bus system uses separate clocks for arbitration and data transfer. The arbitration clock signal is used for synchronizing bus request and grant events, and the data clock signal is used for synchronizing data transmission and reception. In particular, the data clock signal, which is generated by a bus master node without any temporal relationship to the arbitration clock signal, is transmitted by the bus master node through the bus to a slave node, where the received data signal is synchronized with the data clock signal transmitted therewith.
摘要翻译： 总线系统使用单独的时钟进行仲裁和数据传输。 仲裁时钟信号用于同步总线请求和授权事件，并且数据时钟信号用于同步数据发送和接收。 特别地，由总线主节点生成的与仲裁时钟信号没有任何时间关系的数据时钟信号由总线主节点通过总线传输到从节点，其中所接收的数据信号与 数据时钟信号。
-
公开(公告)号：US5473762A
公开(公告)日：1995-12-05
申请号：US186381
申请日：1994-01-25
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： A system for pipelining bus requests includes a bus, at least one node coupled to the bus, and a bus coordinator coupled to the node. The node uses a single bus request signal to both request control of the bus from the bus coordinator, and to retain control of the bus. In response to an asserted bus request signal from the node, the coordinator sends an asserted bus grant signal to the node to grant the node control of the bus. This bus grant signal tracks the bus request signal so that as long as the bus request signal remains asserted, the bus grant signal also is asserted. To allow for pipelining, the bus coordinator maintains the bus grant signal in an asserted state for at least one clock cycle after the bus request is deasserted. By holding the bus grant signal in the asserted state for one extra cycle, the coordinator gives the node time to deassert and then to reassert the bus request signal before the bus grant signal changes state. If the bus request is reasserted within the extra cycle, the coordinator continues to maintain the bus grant signal in the asserted state so that no state change is experienced by the bus grant signal between the deassertion and the reassertion of the bus request signal. In this manner, consecutive bus requests are pipelined. To further increase the efficiency of the system, the node deasserts the bus request signal at least one clock cycle before it send its last set of information, and continues to send information signals in the following clock cycle. By so doing, the node ensures that the extra clock cycle of the bus grant is not wasted.
摘要翻译： 用于流水线总线请求的系统包括总线，耦合到总线的至少一个节点和耦合到该节点的总线协调器。 节点使用单个总线请求信号来从总线协调器请求总线的控制，并保持对总线的控制。 响应于来自节点的断言的总线请求信号，协调器向节点发送断言的总线许可信号以授予节点对总线的控制。 该总线授权信号跟踪总线请求信号，使得只要总线请求信号保持有效，总线授权信号也被断言。 为了允许流水线化，总线协调器在总线请求被取消置位之后至少将一个时钟周期维持在断言状态。 通过将总线授权信号保持在断言状态一个额外的周期，协调器给出节点的时间，以在总线授权信号改变状态之前重新发送总线请求信号。 如果总线请求在额外的周期内重新生效，则协调器继续将总线授权信号维持在断言状态，使得总线授权信号在总线授权信号在总线请求信号和重新发送总线请求信号之间不会发生变化。 以这种方式，连续的总线请求被流水线化。 为了进一步提高系统的效率，节点在发送其最后一组信息之前，至少将一个时钟周期取消总线请求信号的发信号，并在随后的时钟周期继续发送信息信号。 通过这样做，节点确保总线授权的额外时钟周期不被浪费。
-
公开(公告)号：US5469435A
公开(公告)日：1995-11-21
申请号：US187396
申请日：1994-01-25
IPC分类号： G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： Signal transactions are conducted between nodes coupled to a bus, without causing bus deadlock during split transactions. Deadlock avoidance is achieved by rendering a node effectively unavailable at such times to serve as a bus slave for a new bus master. When the "locking" node serves as a transaction source, deadlock is avoided by deasserting, during a split transaction, a buffer-available signal, which is used normally to indicate receiver buffer availability. Additionally, when the "locking" node serves as a transaction destination, deadlock is avoided by deasserting a bus-ownership request signal, which is used normally for requesting bus ownership. After completion of the split transactions, such signals may be unmasked.
摘要翻译： 信号事务在耦合到总线的节点之间进行，而不会在分离事务期间导致总线死锁。 通过使节点在这样的时间有效地不可用来作为新总线主机的总线从设备来实现死锁避免。 当“锁定”节点用作事务源时，通过在分离事务期间解除缓冲器可用信号来解除死锁，通常用于指示接收器缓冲区可用性。 另外，当“锁定”节点用作事务目的地时，通过解除总线所有权请求信号（通常用于请求总线所有权）来避免死锁。 拆分事务完成后，这些信号可能被屏蔽。
-
6.发明授权Interconnect system initiating data transfer over launch bus at source's clock speed and transfering data over data path at receiver's clock speed 失效互连系统通过发射总线以源的时钟速度启动数据传输，并以接收机的时钟速度在数据路径上传输数据
公开(公告)号：US5640599A
公开(公告)日：1997-06-17
申请号：US210733
申请日：1994-03-18
CPC分类号： G06F15/17
摘要： A computer interconnect including a plurality of nodes, each node capable of joining to a component of a computer, each node including apparatus for transferring signals between the component and the node, apparatus for storing packets of data, apparatus for signalling each other node that a packet of data exists for transfer to a component associated with that node, apparatus for sensing signals from another node indicating that a packet of data exists for transfer to a component associated with that node, and apparatus for transferring packets of data stored at one node to the apparatus for transferring signals between the component and the node of another node.
摘要翻译： 一种包括多个节点的计算机互连，每个节点能够加入到计算机的组件，每个节点包括用于在组件和节点之间传送信号的装置，用于存储数据分组的装置，用于发信号通知每个其他节点的装置 存在用于传送到与该节点相关联的组件的数据分组的装置，用于感测来自另一个节点的信号的装置，指示存在用于传送到与该节点相关联的组件的数据分组的数据;以及用于将存储在一个节点的数据分组传送到 用于在组件和另一节点的节点之间传送信号的装置。
-
7.发明授权System for providing control of data transmission by destination node using stream values transmitted from plural source nodes 失效用于使用从多个源节点发送的流值来提供目的地节点对数据传输的控制的系统
公开(公告)号：US5694545A
公开(公告)日：1997-12-02
申请号：US483831
申请日：1995-06-07
IPC分类号： G06F13/00 , G06F13/18 , H04N7/173 , G06F13/362
CPC分类号： H04N7/17336 , G06F13/18
摘要： Apparatus for allowing a component of a computer system to which data is to be written to control the order of transfer of that data including circuitry for providing a numbered signal signifying that a particular component has a set of data which is to be transferred to the destination component, circuitry associated with the destination component for choosing among all of the numbered signals to select from all sets of data a next set of data in a particular numerical order, and circuitry associated with the destination component for selecting other than the next set of data in the particular numerical order.
摘要翻译： 用于允许要写入数据的计算机系统的组件以控制该数据的传送顺序的装置，包括用于提供编号的信号的电路，该电路指示特定组件具有要传送到目的地的一组数据 与目的地组件相关联的电路，用于在所有编号的信号中选择以从特定数字顺序的下一组数据的所有数据集中选择的电路，以及与用于选择下一组数据的目的地组件相关联的电路 在特定的数字顺序。
-
8.发明授权Method for semaphore communication between incompatible bus locking architectures 失效不兼容总线锁定架构之间信号通信的方法
公开(公告)号：US5548780A
公开(公告)日：1996-08-20
申请号：US278264
申请日：1994-07-21
申请人： William T. Krein
发明人： William T. Krein
CPC分类号： G06F13/4036
摘要： A semaphore method establishes exclusive access transactions between source and destination nodes in a multiple bus computer system, independent of the bus locking architectures of the component buses. An atomic transaction is selected for each bus protocol to mediate exclusive access transactions involving the corresponding bus, and bridges coupling different pairs of buses monitor these buses for the selected atomic transactions. A source node on one bus (the source bus) initiates an exclusive access transaction to a destination node by launching the selected atomic transaction appropriate for the source bus to the destination node. When the path between the source and the destination nodes requires transit of more than one bus, each bridge that couples a pair of buses in the path detects an incoming atomic transaction on one of these buses and launches an outgoing atomic transactions appropriate for the other bus to the destination node. In this way, the atomic transaction initiated by the source node to establish an exclusive transaction with the destination node is coupled through the buses of the system by a series of selected atomic transactions. Since each bus supports at least one atomic transaction, the semaphore method operates effectively, independent of the bus locking architectures of the buses.
摘要翻译： 信号量方法在多总线计算机系统中的源节点和目的节点之间建立独占访问事务，独立于组件总线的总线锁定架构。 为每个总线协议选择原子事务以介入涉及相应总线的独占访问事务，以及耦合不同对总线监视所选原子事务的这些总线的桥。 一个总线（源总线）上的源节点通过将适合于源总线的所选择的原子事务启动到目的地节点，来向目的地节点发起独占访问事务。 当源节点和目的节点之间的路径需要传输多于一条总线时，在路径中耦合一对总线的每个网桥将检测其中一条总线上的进入原子事务，并启动适用于另一条总线的输出原子事务 到目标节点。 以这种方式，由源节点发起的用于与目的地节点建立独占事务的原子事务通过系列的总线通过一系列选定的原子事务耦合。 由于每个总线支持至少一个原子事务，所以信号量方法有效地运行，而与总线的总线锁定架构无关。
-
9.再颁专利System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer 有权用于从设备接收用于选择其相关联的时钟信号以控制经由缓冲器传送信息的控制信号的系统公开(公告)号：USRE40317E1
公开(公告)日：2008-05-13
申请号：US09815873
申请日：2001-03-22
IPC分类号： G06F13/00
CPC分类号： G06F13/4243
摘要： A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component to the apparatus for storing information utilizing the clock of the first component, a second component operated in response to the timing of a second clock, apparatus for utilizing the clock of the second component to transfer information from the apparatus for storing information in a condition in which it is synchronized for use by the second component whereby the information may be immediately utilized by the second component without the need for storage by the second component.
摘要翻译： 一种计算机系统，包括响应于第一时钟的定时操作的第一组件，用于存储信息的设备，用于将信息从第一组件传输到利用第一组件的时钟存储信息的设备的设备， 响应于第二时钟的定时，用于利用第二组件的时钟从用于存储信息的设备传送信息的设备在其被同步以供第二组件使用的条件下的设备，由此信息可以被第二时钟的定时利用 第二组件，而不需要由第二组件存储。
-
10.发明授权Apparatus for providing priority arbitration in a computer system interconnect 失效用于在计算机系统互连中提供优先仲裁的装置
公开(公告)号：US5257385A
公开(公告)日：1993-10-26
申请号：US815825
申请日：1991-12-30
IPC分类号： G06F13/14
CPC分类号： G06F13/14
摘要： A circuit which includes apparatus for determining for at each node of a multi-node interconnect the highest priority data present for transfer to that node, apparatus for storing information indicating the last node from which a transfer of data occurred at each priority level, apparatus for selecting for each priority level of data available at the node the last node from which a transfer of data occurred at each priority level, apparatus for weighting data at each priority level depending on the data last chosen at that level of priority, and means for selecting from all of the data available at each node the data having both the highest priority and having been chosen least recently at that priority levels of data at that node.
摘要翻译： 一种电路，包括用于在多节点互连的每个节点处确定用于传送到该节点的最高优先级数据的装置，用于存储指示在每个优先级级别发生数据传输的最后节点的信息的装置，用于 选择在节点处可用于每个优先级级别的数据传输的最后节点的每个优先级数据的装置，用于根据在该优先级级别最后选择的数据在每个优先级处加权数据的装置，以及用于选择 从每个节点可用的所有数据中，数据具有最高优先级并且最近被选择在该节点处的那个优先级数据。
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.022 秒)
