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    MEMORY TESTING SYSTEM
    1.
    发明申请
    MEMORY TESTING SYSTEM 有权
    内存测试系统

    公开(公告)号：US20110307747A1

    公开(公告)日：2011-12-15

    申请号：US12797181

    申请日：2010-06-09

    申请人： Kevin J. Duffy ,  William V. Huott ,  Pradip Patel ,  Daniel Rodko

    发明人： Kevin J. Duffy ,  William V. Huott ,  Pradip Patel ,  Daniel Rodko

    IPC分类号： G11C29/04 ,  G06F11/22

    CPC分类号： G11C29/32 ,  G11C11/41

    摘要： An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch.

    摘要翻译： 阵列内置自检（ABIST）系统包括具有第一数据输入，第一扫描输入和第一输出的第一锁存器以及具有第二数据输入的第二锁存器，第二扫描输入端和第二输出端。 该系统还包括耦合到第一输出的第一ABIST逻辑块，该第一ABIST逻辑块将第一预期值与在第一数据输入端接收的第一数据值进行比较，并在第一时钟施加到第一锁存器之后提供给第一ABIST逻辑块。 该系统还包括耦合到第二输出的第二ABIST逻辑块，该第二ABIST逻辑块将第二预期值与在第二数据输入端接收的第二数据值进行比较，并在第二时钟施加到第二锁存器之后提供给第二ABIST逻辑块。

    Array self repair using built-in self test techniques
    2.
    发明授权
    Array self repair using built-in self test techniques 失效
    使用内置自检技术进行阵列自修复

    公开(公告)号：US07257745B2

    公开(公告)日：2007-08-14

    申请号：US11047419

    申请日：2005-01-31

    申请人： William V. Huott ,  Franco Motika ,  Pradip Patel ,  Daniel Rodko

    发明人： William V. Huott ,  Franco Motika ,  Pradip Patel ,  Daniel Rodko

    IPC分类号： G11C29/00 ,  G01R31/28 ,  G11C17/18

    CPC分类号： G01R31/318572 ,  G01R31/318566

    摘要： A soft-fust test algorithm is distributed on-chip from an ABSIT engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Using single-bit MISR error evaluation an ABSIT test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.

    摘要翻译： 软测试算法通过LSSD移位寄存器链从ABSIT引擎分布在片上，以动态评估多个阵列，对不良元素进行冗余补偿，并修复可修复的阵列。 使用单位MISR错误评估，通过移位寄存器链在所有数组上同时执行一个ABSIT测试序列。 如果任何阵列出现错误，则采用冗余补偿，并对所有可能的阵列冗余组合重复ABIST测试，直到每个阵列的功能配置被识别或已尝试所有可能的冗余组合。 一旦功能阵列配置被验证，相关联的软保险丝状态可以用于熔断和/或提取用于进一步的系统设置，永久保险丝熔断和产量分析。 可能需要由单独的ABIST引擎驱动的多个移位寄存器链来测试芯片上的所有阵列。

    Memory testing system
    3.
    发明授权
    Memory testing system 有权
    内存测试系统

    公开(公告)号：US08327207B2

    公开(公告)日：2012-12-04

    申请号：US12797181

    申请日：2010-06-09

    申请人： Kevin J. Duffy ,  William V. Huott ,  Pradip Patel ,  Daniel Rodko

    发明人： Kevin J. Duffy ,  William V. Huott ,  Pradip Patel ,  Daniel Rodko

    IPC分类号： G01R31/28

    CPC分类号： G11C29/32 ,  G11C11/41

    摘要： An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch.

    摘要翻译： 阵列内置自检（ABIST）系统包括具有第一数据输入，第一扫描输入和第一输出的第一锁存器以及具有第二数据输入的第二锁存器，第二扫描输入端和第二输出端。 该系统还包括耦合到第一输出的第一ABIST逻辑块，该第一ABIST逻辑块将第一预期值与在第一数据输入端接收的第一数据值进行比较，并在第一时钟施加到第一锁存器之后提供给第一ABIST逻辑块。 该系统还包括耦合到第二输出的第二ABIST逻辑块，该第二ABIST逻辑块将第二预期值与在第二数据输入端接收的第二数据值进行比较，并在第二时钟施加到第二锁存器之后提供给第二ABIST逻辑块。

    Clock duty cycle based access timer combined with standard stage clocked output register
    6.
    发明授权
    Clock duty cycle based access timer combined with standard stage clocked output register 失效
    基于时钟占空比的访问定时器与标准级时钟输出寄存器相结合

    公开(公告)号：US07275194B2

    公开(公告)日：2007-09-25

    申请号：US11057318

    申请日：2005-02-11

    申请人： William V. Huott ,  Pradip Patel ,  Daniel Rodko

    发明人： William V. Huott ,  Pradip Patel ,  Daniel Rodko

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3187 ,  G01R31/31727

    摘要： An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.

    摘要翻译： 被测元件的输出通过多路复用器捕获并存储在捕获寄存器中。 在时钟边沿（上升沿或下降沿），被测元件会捕获“边沿”并“输入”输出。 选通多路复用器，并测量延迟和占空比。 上升沿和下降沿均用作定时器。

    Array self repair using built-in self test techniques
    7.
    发明申请
    Array self repair using built-in self test techniques 失效
    使用内置自检技术进行阵列自修复

    公开(公告)号：US20060174175A1

    公开(公告)日：2006-08-03

    申请号：US11047419

    申请日：2005-01-31

    申请人： William Huott ,  Franco Motika ,  Pradip Patel ,  Daniel Rodko

    发明人： William Huott ,  Franco Motika ,  Pradip Patel ,  Daniel Rodko

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318572 ,  G01R31/318566

    摘要： A soft-fuse test algorithm is distributed on-chip from an ABIST engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Each arrays outputs are monitored by a different multiple input signature register (MISR) with an initial data pattern seed that provides a final desired state of the MISR with either all “0”s or all “1”s, allowing for a simple “single-bit” MISR error evaluation of the monitored array. Using the above single-bit MISR error evaluation technique an ABIST test sequence is executed concurrently on all arrays through the shift register chain. If any arrays are in error, redundancy compensation is employed and the ABIST test is repeated for all possible array redundant combinations until a functional configuration for each array is identified or all possible redundant combinations have been tried. Once functioning array configurations are verified, the associated soft-fuse states can be used to blow fuses and/or extracted for further system setup, permanent fuse-blowing and yield analysis. Multiple shift register chains driven by separate ABIST engines may be required to test all arrays on a chip.

    摘要翻译： 软保险丝测试算法通过LSSD移位寄存器链从ABIST引擎分布在片上，以动态评估多个阵列，对坏元素进行冗余补偿，并修复可修复的阵列。 每个阵列输出由具有初始数据模式种子的不同的多输入签名寄存器（MISR）监视，提供MISR的所有“0”或全“1”的最终期望状态，允许简单的“单 -bit“监控阵列的MISR错误评估。 使用上述单位MISR错误评估技术，通过移位寄存器链在所有阵列上同时执行ABIST测试序列。 如果任何阵列出现错误，则采用冗余补偿，并对所有可能的阵列冗余组合重复ABIST测试，直到每个阵列的功能配置被识别或已尝试所有可能的冗余组合。 一旦功能阵列配置被验证，相关联的软保险丝状态可以用于熔断和/或提取用于进一步的系统设置，永久保险丝熔断和产量分析。 可能需要由单独的ABIST引擎驱动的多个移位寄存器链来测试芯片上的所有阵列。

    BIST address generation architecture for multi-port memories
    8.
    发明申请
    BIST address generation architecture for multi-port memories 失效
    用于多端口存储器的BIST地址生成架构

    公开(公告)号：US20050268167A1

    公开(公告)日：2005-12-01

    申请号：US10843608

    申请日：2004-05-11

    申请人： William Huott ,  Pradip Patel ,  Daniel Rodko

    发明人： William Huott ,  Pradip Patel ,  Daniel Rodko

    IPC分类号： G06F11/00 ,  G06F11/27

    CPC分类号： G06F11/27

    摘要： Disclosed is testing multi-port array macros where latches and logic are used to control the relationship between the write and read port of the array. This makes allowance for many different configurations of reading and writing the array. This also allows for greater test coverage than the previous method, which simply inverted one of the write address bits to form the read address.

    摘要翻译： 公开了测试多端口阵列宏，其中使用锁存器和逻辑来控制阵列的写入和读取端口之间的关系。 这使得读取和写入阵列的许多不同配置成为可能。 这也允许比以前的方法更大的测试覆盖率，其简单地将写入地址位之一反转以形成读取地址。

    BIST address generation architecture for multi-port memories
    9.
    发明授权
    BIST address generation architecture for multi-port memories 失效
    用于多端口存储器的BIST地址生成架构

    公开(公告)号：US07536613B2

    公开(公告)日：2009-05-19

    申请号：US10843608

    申请日：2004-05-11

    申请人： William Vincent Huott ,  Pradip Patel ,  Daniel Rodko

    发明人： William Vincent Huott ,  Pradip Patel ,  Daniel Rodko

    IPC分类号： G11C29/00 ,  G11C7/10

    CPC分类号： G06F11/27

    摘要： Disclosed is testing multi-port array macros where latches and logic are used to control the relationship between the write and read port of the array. This makes allowance for many different configurations of reading and writing the array. This also allows for greater test coverage than the previous method, which simply inverted one of the write address bits to form the read address.

    摘要翻译： 公开了测试多端口阵列宏，其中使用锁存器和逻辑来控制阵列的写入和读取端口之间的关系。 这使得读取和写入阵列的许多不同配置成为可能。 这也允许比以前的方法更大的测试覆盖率，其简单地将写入地址位之一反转以形成读取地址。