公开(公告)号：US3936929A

公开(公告)日：1976-02-10

申请号：US483264

申请日：1974-06-26

Applicant: Kenneth E. Bean ,  William W. Lloyd

Inventor： Kenneth E. Bean ,  William W. Lloyd

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/00 ,  B01J17/00

CPC classification number: H01L27/0623 ,  H01L21/76264 ,  H01L21/764 ,  H01L21/8248 ,  H01L21/8249 ,  H01L29/00 ,  H01L21/76289 ,  Y10S148/051 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/102 ,  Y10S148/145

Abstract: Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and resistivity control, and an orientation dependent etch forms grooves circumscribing portions of the host substrate and overlying epitaxial layers to provide dielectrically isolated single crystalline mesas utilized in forming electronic devices.This is a division of application Ser. No. 275,116, filed July 26, 1972.

Abstract translation: 公开了改进的场效应和双极半导体器件及其制造方法，其中最大接点控制提供高度可预测的器件参数。 低温外延沉积提供紧密的结厚度和电阻率控制，并且取向依赖的蚀刻形成限定主体衬底和上覆外延层的部分的凹槽，以提供用于形成电子器件的介电隔离的单晶台面。

公开(公告)号：US4063271A

公开(公告)日：1977-12-13

申请号：US275116

申请日：1972-07-26

Applicant: Kenneth E. Bean ,  William W. Lloyd

Inventor： Kenneth E. Bean ,  William W. Lloyd

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/8232 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/00 ,  H01L29/08 ,  H01L27/12 ,  H01L27/02 ,  H01L29/06 ,  H01L29/80

CPC classification number: H01L29/0821 ,  H01L21/76264 ,  H01L21/764 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/00 ,  H01L21/76289 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/115

Abstract: Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and resistivity control, and an orientation dependent etch forms grooves circumscribing portions of the host substrate and overlying epitaxial layers to provide dielectrically isolated single crystalline mesas utilized in forming electronic devices.

Abstract translation: 公开了改进的场效应和双极半导体器件及其制造方法，其中最大结点控制提供高度可预测的器件参数。 低温外延沉积提供紧密的结厚度和电阻率控制，并且取向依赖的蚀刻形成限定主体衬底和上覆外延层的部分的凹槽，以提供用于形成电子器件的介电隔离的单晶台面。

公开(公告)号：US4462027A

公开(公告)日：1984-07-24

申请号：US121951

申请日：1980-02-15

Applicant: William W. Lloyd

Inventor： William W. Lloyd

IPC: G02F1/133 ,  G09G3/36 ,  G09G3/18

CPC classification number: G02F1/133382 ,  G09G3/3622 ,  G09G3/3681 ,  G09G2320/041

Abstract: A system and method for controlling the effective root mean square (RMS) voltage (Veff) across the segments of a liquid crystal display as a function of the frequency of the voltage signal applied thereto and selected parameters of the display package are described. Display parameters such as the thickness of the barrier dielectric layer and the electrical resistance of the liquid crystal material are chosen so that the ON and OFF states of the display are selectively controllable by lowering the frequency of the drive voltage signal applied to the OFF segments (Foff) a predetermined amount below that of the drive voltage signal applied to the ON segments (Fon), thereby decreasing the ratio of the effective RMS voltage Veff to the RMS voltage of the applied voltage signal (Vapp) for the OFF segments as compared to the ratio Veff/Vapp for the ON segments. The number of drive lines which can be effectively multiplexed is thereby increased. By proper selection of drive frequencies and other display parameters, temperature compensation without the need for additional sensors and circuitry is also achieved.

Abstract translation: 描述了作为施加到其上的电压信号的频率和显示包的选定参数的函数的用于控制液晶显示器的段的有效均方根（RMS）电压（Veff）的系统和方法。 选择诸如屏障介电层的厚度和液晶材料的电阻的显示参数，使得通过降低施加到OFF段的驱动电压信号的频率来选择性地控制显示器的ON和OFF状态（ Foff），其预定量低于施加到ON段（Fon）的驱动电压信号的预定量，从而减小与段分压相比，OFF段的有效RMS电压Veff与施加电压信号（Vapp）的RMS电压的比率 ON段的Veff / Vapp比。 从而可以有效地多路复用的驱动线的数量增加。 通过适当选择驱动频率和其他显示参数，也可实现温度补偿，无需额外的传感器和电路。

公开(公告)号：US3936346A

公开(公告)日：1976-02-03

申请号：US428266

申请日：1973-12-26

Applicant: William W. Lloyd

Inventor： William W. Lloyd

IPC: C30B13/20 ,  C30B15/02 ,  C30B15/10 ,  C30B15/14 ,  B01J17/10

CPC classification number: C30B15/02 ,  C30B13/20 ,  C30B15/10 ,  C30B15/14 ,  Y10S117/90

Abstract: The disclosure relates to the growth of single crystal material from polycrystalline material by combining the pedestal and cold crucible techniques to yield a method of producing large, high purity single crystals on a commercial scale. The method includes feeding a bar of polycrystalline material, such as silicon, into a cold cage which can be a cold silver crucible or the like having an aperture in the bottom thereof to permit insertion of the polycrystalline feed bar. An RF coil surrounds the cold cage and melts the silicon as it reaches into the cage, the RF coil providing a temperature to the silicon material which is slightly above the melting point thereof. A rod of single crystal material, the same as the feed bar, is positioned in the melt from the top surface of the cold cage and acts as a seed crystal. The single crystal rod is then pulled upwardly from the cage while polycrystalline silicon is fed into the cage through the aperture in the bottom thereof. By continuously forcing the polycrystalline rod into the cage and pulling a rod at the top of the cage, a large single crystal can be grown while maintaining only a small melt volume. The diameter of the single crystal rod being pulled will have a relation to the upper diameter of the cold cage as well as the ratio of the feed rate of the polycrystalline bar relative to the pull rate of the single crystalline bar.

Abstract translation: 本公开涉及通过组合基座和冷坩埚技术从多晶材料生长单晶材料，以产生在商业规模上生产大的高纯度单晶的方法。 该方法包括将诸如硅的多晶材料棒放入冷笼中，该冷笼可以是在其底部具有孔的冷银坩埚等以允许多晶进料棒的插入。 RF线圈围绕冷笼并在硅到达保持架时熔化硅，RF线圈向硅材料提供略高于其熔点的温度。 与进料棒相同的单晶材料棒从冷笼的顶表面定位在熔体中并用作晶种。 然后将单晶棒从保持架向上拉，而多晶硅通过其底部的孔进入保持架。 通过将多晶棒连续地强制进入保持架并拉动保持架顶部的杆，可以生长大的单晶，同时只保持较小的熔体体积。 被拉动的单晶棒的直径将与冷笼的上直径以及多晶棒的进料速率相对于单晶棒的拉伸速率的比率有关。