公开(公告)号：US06274916B1

公开(公告)日：2001-08-14

申请号：US09443367

申请日：1999-11-19

申请人： Wilm E. Donath ,  Dennis M. Newns ,  Pratap C. Pattnaik

发明人： Wilm E. Donath ,  Dennis M. Newns ,  Pratap C. Pattnaik

IPC分类号： H01L3300

CPC分类号： H01L49/003

摘要： A method and structure for a field effect transistor (FET) includes a source region, a drain region, a channel region extending between the source region and the drain region, a gate region, and a gate oxide region separating the gate region from other regions of the FET. The channel region is a Mott insulator. The gate oxide region is thicker than the channel region, and the gate oxide region includes a higher dielectric permittivity than the Mott insulator material.

摘要翻译： 场效应晶体管（FET）的方法和结构包括源极区域，漏极区域，在源极区域和漏极区域之间延伸的沟道区域，栅极区域和将栅极区域与其它区域分离的栅极氧化物区域 的FET。 通道区域是Mott绝缘体。 栅极氧化物区域比沟道区域厚，并且栅极氧化物区域具有比Mott绝缘体材料更高的介电常数。

公开(公告)号：US07519777B1

公开(公告)日：2009-04-14

申请号：US12136808

申请日：2008-06-11

申请人： Kattamuri Ekanadham ,  Il Park ,  Pratap C. Pattnaik

发明人： Kattamuri Ekanadham ,  Il Park ,  Pratap C. Pattnaik

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/30 ,  G06F9/40 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F12/0862 ,  G06F9/3455 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3848 ,  G06F2212/6026

摘要： Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride pattern, detecting an indirect access pattern to define an access window, prefetching candidates within the defined access window, wherein the prefetching comprises obtaining prefetch addresses from a history table, updating a miss stream window, selecting a candidate of a concomitant pair from the miss stream window, producing an index from the candidate pair, accessing an aging filter, updating the history table and selecting another concomitant pair candidate from the miss stream window.

摘要翻译： 方法，系统和计算机程序产品，用于伴随对提取。 示例性实施例包括用于并发对预取的方法，所述方法包括检测步幅模式，检测间接访问模式以定义访问窗口，在定义的访问窗口内预取候选，其中预取包括从历史表获取预取地址，更新 错过流窗口，从缺失流窗口中选择伴随对的候选，从候选对产生索引，访问老化过滤器，更新历史表并从缺失流窗口中选择另一个伴随对候选者。

公开(公告)号：US06178174B1

公开(公告)日：2001-01-23

申请号：US08918390

申请日：1997-08-26

申请人： Hubertus Franke ,  Rama K. Govindaraju ,  Pratap C. Pattnaik ,  Mandayam T. Raghunath ,  Robert M. Straub

发明人： Hubertus Franke ,  Rama K. Govindaraju ,  Pratap C. Pattnaik ,  Mandayam T. Raghunath ,  Robert M. Straub

IPC分类号： H04L1254

CPC分类号： H04L47/10 ,  H04L47/30

摘要： A method, system, and associated program code and data structures are provided for a message processing system in which messages are transmitted from source nodes to destination nodes. An “eager” rendezvous transmission mode is disclosed in which early arrival buffering is provided at message destination nodes for a predetermined amount of data for each of a predetermined number of incoming messages. Relying on the presence of the early arrival buffering at a message destination node, a message source node can send a corresponding amount of message data to the destination node along with control information in an initial transmission. Any remaining message data is sent only upon receipt by the source node of an acknowledgement from the destination node indicating that the destination node is prepared to receive any remaining data. In an enhanced embodiment, the source node alternates between rendezvous transmission modes as a function of the amount of free space in the early arrival buffering at the destination node, as indicated by the number of outstanding initial transmissions for which acknowledgements have not yet been received. Different transmission modes for different destination nodes can be employed at a source node, depending on the amount of early arrival buffering currently available in each respective destination node.

摘要翻译： 提供了一种消息处理系统的方法，系统和相关联的程序代码和数据结构，其中消息从源节点传送到目的地节点。 公开了一种“急切的”会合传输模式，其中针对预定数量的进入消息中的每一个为预定量的数据在消息目的地节点处提供早到达缓冲。 依赖于在消息目的地节点处的早期到达缓冲的存在，消息源节点可以在初始传输中与控制信息一起向目的地节点发送相应量的消息数据。 任何剩余的消息数据仅在源节点收到来自目的地节点的确认时发送，指示目的地节点准备接收任何剩余数据。 在增强实施例中，源节点在集合传输模式之间交替，作为在目的地节点处的早到达缓冲中的可用空间量的函数，如尚未被接收到确认的未完成初始传输的数量所指示的。 根据当前在每个相应目的地节点中可用的早到达缓冲的数量，可以在源节点采用用于不同目的地节点的不同传输模式。

公开(公告)号：US08683175B2

公开(公告)日：2014-03-25

申请号：US13048214

申请日：2011-03-15

申请人： Kattamuri Ekanadham ,  Hung Q. Le ,  Jose E. Moreira ,  Pratap C. Pattnaik

发明人： Kattamuri Ekanadham ,  Hung Q. Le ,  Jose E. Moreira ,  Pratap C. Pattnaik

IPC分类号： G06F9/30 ,  G06F12/10

CPC分类号： G06F9/3877 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3851 ,  G06F12/1027

摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.

摘要翻译： 公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。 在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换 。 只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。 这有助于启动指定的操作，而不会出现内存转换错误。 在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

公开(公告)号：US06297729B1

公开(公告)日：2001-10-02

申请号：US09280961

申请日：1999-03-29

申请人： Bulent Abali ,  Hubertus Franke ,  Mark E. Giampapa ,  Pratap C. Pattnaik

发明人： Bulent Abali ,  Hubertus Franke ,  Mark E. Giampapa ,  Pratap C. Pattnaik

IPC分类号： H04M1104

CPC分类号： H04L63/02 ,  H04B3/542 ,  H04B2203/5425 ,  H04B2203/5458 ,  H04B2203/5491 ,  H04L12/10 ,  H04L12/22

摘要： A power line communications system including a power line for supplying ac power; a power source connected to the power line at one end; and a communications network having a plurality of devices, the devices connected to the power line at another end for (a) receiving ac power and (b) communicating information. The system also includes a security firewall coupled between the one end and the other end of the power line for securing the communications information. The security firewall passes the ac power without attenuation, but blocks the communications information from passing. The security firewall also prevents passage of interference to the communications network. In this manner a secure and interference-free communications network is established.

摘要翻译： 一种电力线通信系统，包括用于提供交流电力的电力线; 在一端连接到电源线的电源; 以及具有多个设备的通信网络，所述设备在另一端连接到电力线，用于（a）接收交流电力和（b）传达信息。 该系统还包括耦合在电力线的一端和另一端之间的安全防火墙，用于保护通信信息。 安全防火墙通过交流电源无衰减，但阻止通信信息传递。 安全防火墙还可以防止对通信网络的干扰。 以这种方式，建立了安全且无干扰的通信网络。

公开(公告)号：US07409535B2

公开(公告)日：2008-08-05

申请号：US11110240

申请日：2005-04-20

申请人： Il Park ,  Pratap C. Pattnaik ,  Jong-Deok Choi

发明人： Il Park ,  Pratap C. Pattnaik ,  Jong-Deok Choi

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/30061 ,  G06F9/324

摘要： An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-target branch and logic for reading the memory and identifying a repeated pattern in a plurality of target addresses for a multi-target branch. The information processing system further includes logic for predicting a next target address for the multi-target branch based on the repeated pattern that was identified.

摘要翻译： 公开了一种用于分支目标预测的信息处理系统。 信息处理系统包括用于存储条目的存储器，其中每个条目包括表示多目标分支的目标地址的历史的多个目标地址和用于读取存储器的逻辑，以及识别多个目标地址中的重复模式， 多目标分支。 信息处理系统还包括用于基于所识别的重复模式预测多目标分支的下一目标地址的逻辑。

公开(公告)号：US08850410B2

公开(公告)日：2014-09-30

申请号：US12696879

申请日：2010-01-29

申请人： Ramanjaneya S. Burugula ,  Joefon Jann ,  Pratap C. Pattnaik

发明人： Ramanjaneya S. Burugula ,  Joefon Jann ,  Pratap C. Pattnaik

IPC分类号： G06F9/45 ,  G06F9/44 ,  G06F9/30 ,  G06F9/00

CPC分类号： G06F9/00 ,  G06F9/3836

摘要： A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of processors, a plurality of code-blocks, and a marker associated with each code-block. The system may also include a special hardware register (code-block marker hardware register) in each processor for identifying the markers of the code-blocks executed by the processor, without changing any of the plurality of code-blocks.

摘要翻译： 一种通过将唯一标记与每个软件代码块相关联来提高软件可维护性，性能和/或安全性的系统和方法; 所述系统包括多个处理器，多个代码块和与每个代码块相关联的标记。 该系统还可以包括用于识别由处理器执行的代码块的标记的每个处理器中的特殊硬件寄存器（代码块标记硬件寄存器），而不改变多个代码块中的任一个。

公开(公告)号：US20120239904A1

公开(公告)日：2012-09-20

申请号：US13048214

申请日：2011-03-15

申请人： Kattamuri Ekanadham ,  Hung Q. Le ,  Jose E. Moreira ,  Pratap C. Pattnaik

发明人： Kattamuri Ekanadham ,  Hung Q. Le ,  Jose E. Moreira ,  Pratap C. Pattnaik

IPC分类号： G06F9/30 ,  G06F12/10

CPC分类号： G06F9/3877 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3851 ,  G06F12/1027

摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.

摘要翻译： 公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。 在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换 。 只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。 这有助于启动指定的操作而不会出现内存转换错误 在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

公开(公告)号：US06542513B1

公开(公告)日：2003-04-01

申请号：US09613072

申请日：2000-07-10

申请人： Hubertus Franke ,  Rama K. Govindaraju ,  Pratap C. Pattnaik ,  Mandayam T. Raghunath ,  Robert M. Straub

发明人： Hubertus Franke ,  Rama K. Govindaraju ,  Pratap C. Pattnaik ,  Mandayam T. Raghunath ,  Robert M. Straub

IPC分类号： H04L1254

CPC分类号： H04L47/10 ,  H04L47/30

摘要： A method, system, and associated program code and data structures are provided for a message processing system in which messages are transmitted from source nodes to destination nodes. An “eager” rendezvous transmission mode is disclosed in which early arrival buffering is provided at message destination nodes for a predetermined amount of data for each of a predetermined number of incoming messages. Relying on the presence of the early arrival buffering at a message destination node, a message source node can send a corresponding amount of message data to the destination node along with control information in an initial transmission. Any remaining message data is sent only upon receipt by the source node of an acknowledgement from the destination node indicating that the destination node is prepared to receive any remaining data. In an enhanced embodiment, the source node alternates between rendezvous transmission modes as a function of the amount of free space in the early arrival buffering at the destination node, as indicated by the number of outstanding initial transmissions for which acknowledgements have not yet been received. Different transmission modes for different destination nodes can be employed at a source node, depending on the amount of early arrival buffering currently available in each respective destination node.

摘要翻译： 提供了一种消息处理系统的方法，系统和相关联的程序代码和数据结构，其中消息从源节点传送到目的地节点。 公开了一种“急切的”会合传输模式，其中针对预定数量的进入消息中的每一个为预定量的数据在消息目的地节点处提供早到达缓冲。 依赖于在消息目的地节点处的早期到达缓冲的存在，消息源节点可以在初始传输中与控制信息一起向目的地节点发送相应量的消息数据。 任何剩余的消息数据仅在源节点收到来自目的地节点的确认时发送，指示目的地节点准备接收任何剩余数据。 在增强实施例中，源节点在集合传输模式之间交替，作为在目的地节点处的早到达缓冲中的可用空间量的函数，如尚未被接收到确认的未完成初始传输的数量所指示的。 根据当前在每个相应目的地节点中可用的早到达缓冲的数量，可以在源节点采用用于不同目的地节点的不同传输模式。

公开(公告)号：US20110191754A1

公开(公告)日：2011-08-04

申请号：US12696879

申请日：2010-01-29

申请人： Ramanjaneya S. Burugula ,  Joefon Jann ,  Pratap C. Pattnaik

发明人： Ramanjaneya S. Burugula ,  Joefon Jann ,  Pratap C. Pattnaik

IPC分类号： G06F9/45 ,  G06F9/00

CPC分类号： G06F9/00 ,  G06F9/3836

摘要： A system and method for improving software maintainability, performance, and/or security by associating a unique marker to each software code-block; the system comprising of a plurality of processors, a plurality of code-blocks, and a marker associated with each code-block. The system may also include a special hardware register (code-block marker hardware register) in each processor for identifying the markers of the code-blocks executed by the processor, without changing any of the plurality of code-blocks.

摘要翻译： 一种通过将唯一标记与每个软件代码块相关联来提高软件可维护性，性能和/或安全性的系统和方法; 所述系统包括多个处理器，多个代码块和与每个代码块相关联的标记。 该系统还可以包括用于识别由处理器执行的代码块的标记的每个处理器中的特殊硬件寄存器（代码块标记硬件寄存器），而不改变多个代码块中的任一个。