公开(公告)号：US06314547B1

公开(公告)日：2001-11-06

申请号：US09152013

申请日：1998-09-11

申请人： Wilm E. Donath ,  Prabhakar N. Kudva

发明人： Wilm E. Donath ,  Prabhakar N. Kudva

IPC分类号： G06F1900

CPC分类号： G06F17/5068

摘要： The method for improving circuit location assignment is capable of operating in the boolean, electrical and spatial (location) domains. Optimization of location assignment parameters can be performed simultaneously by determining a subset of nets or paths and generating sets of motions to improve these nets or paths. Once sets of motions have been generated, they are tested to determine the most beneficial movement for improving the given circuit parameter (e.g., wireability, timing, etc.).

摘要翻译： 用于改善电路位置分配的方法能够在布尔，电和空间（位置）域中操作。 位置分配参数的优化可以通过确定网络或路径的子集并生成运动集来改善这些网络或路径来同时执行。 一旦产生了一组运动，就对它们进行测试，以确定用于改善给定电路参数（例如，可线性，定时等）的最有利的运动。

公开(公告)号：US08949101B2

公开(公告)日：2015-02-03

申请号：US13271827

申请日：2011-10-12

申请人： Pradip Bose ,  Meeta S. Gupta ,  Prabhakar N. Kudva ,  Daniel A. Prener

发明人： Pradip Bose ,  Meeta S. Gupta ,  Prabhakar N. Kudva ,  Daniel A. Prener

IPC分类号： G01R31/3181 ,  G06F17/50 ,  G01R31/3183

CPC分类号： G01R31/31816 ,  G01R31/318357 ,  G06F17/5022

摘要： Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.

摘要翻译： 提供了用于预测软错误对集成电路器件设计的影响的机制。 数据处理系统被配置为实现统一的降额工具，其包括用于生成机器降额信息的机器降额前端引擎和用于生成应用降额信息的应用降级前端引擎用于集成电路器件设计。 机器降额前端引擎执行集成电路设备设计的仿真以生成机器降额信息。 应用降级前端引擎在架构上与集成电路设备设计类似的现有硬件上执行应用程序工作负载，并在执行应用程序工作负载期间将故障注入到现有硬件中，以生成应用程序降级信息。 机器降额信息与应用降级信息组合以产生用于集成电路设备设计的至少一个软错误率值。

公开(公告)号：US08091050B2

公开(公告)日：2012-01-03

申请号：US12243427

申请日：2008-10-01

申请人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

发明人： Pradip Bose ,  Prabhakar N. Kudva ,  Jude A. Rivers ,  Pia N. Sanda ,  John-David Wellman

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5036 ,  G06F2217/82

摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.

摘要翻译： 提供了对软错误的系统级别影响进行建模的机制。 提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。 通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。 在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档 设计。 基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

公开(公告)号：US07930578B2

公开(公告)日：2011-04-19

申请号：US11862559

申请日：2007-09-27

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Zhigang Hu ,  Hans Jacobson ,  Prabhakar N. Kudva ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Zhigang Hu ,  Hans Jacobson ,  Prabhakar N. Kudva ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

IPC分类号： G06F1/00 ,  G06F11/30 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/206 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D50/20

摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.

摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。

公开(公告)号：US07723207B2

公开(公告)日：2010-05-25

申请号：US11737598

申请日：2007-04-19

申请人： Syed M. Alam ,  Ibrahim M. Elfadel ,  Kathryn W Guarini ,  Meikei Ieong ,  Prabhakar N. Kudva ,  David S. Kung ,  Mark A. Lavin ,  Arifur Rahman

发明人： Syed M. Alam ,  Ibrahim M. Elfadel ,  Kathryn W Guarini ,  Meikei Ieong ,  Prabhakar N. Kudva ,  David S. Kung ,  Mark A. Lavin ,  Arifur Rahman

IPC分类号： H01L21/30

CPC分类号： H01L27/0688 ,  H01L21/2007 ,  H01L21/84 ,  H01L27/1203

摘要： A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

摘要翻译： 三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。 该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。 这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

公开(公告)号：US20090070720A1

公开(公告)日：2009-03-12

申请号：US11853276

申请日：2007-09-11

申请人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Lawrence Lange ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri ,  Gebhard Weber

发明人： Reinaldo A. Bergamaschi ,  Sean M. Carey ,  Brian W. Curran ,  Prabhakar N. Kudva ,  Lawrence Lange ,  Matthew E. Mariani ,  Mark D. Mayo ,  Ruchir Puri ,  Gebhard Weber

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison.

摘要翻译： 用于识别由于逻辑块变化引起的时序差异的系统，系统可以包括控制器和与控制器通信的存储器。 控制器可以提供先前逻辑块和当前逻辑块的延迟值。 该系统还可以包括一个定时建模器，用于将先前逻辑块的延迟值与用于定时分析的当前逻辑块进行比较。 系统还可以包括基于先前逻辑块和当前逻辑块比较来提供报告的接口。

公开(公告)号：US07421601B2

公开(公告)日：2008-09-02

申请号：US11357612

申请日：2006-02-17

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Prabhakar N. Kudva

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Prabhakar N. Kudva

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/206 ,  G06F1/3203 ,  Y02D10/16

摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchical architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.

摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每个层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，而较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。

公开(公告)号：US07373615B2

公开(公告)日：2008-05-13

申请号：US10780140

申请日：2004-02-17

申请人： William E. Dougherty, Jr. ,  Victor Kravets ,  Prabhakar N. Kudva ,  Andrew J. Sullivan

发明人： William E. Dougherty, Jr. ,  Victor Kravets ,  Prabhakar N. Kudva ,  Andrew J. Sullivan

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design. Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.

摘要翻译： 随着芯片复杂度的增加，VLSI芯片的可路由性（或布线拥塞）变得越来越重要。 拥塞对性能，产量和芯片面积有重大影响。 本发明在物理设计之前针对技术独立综合早期拥塞的优化。 我们不是试图优化逻辑结构以及电路的空间布局，而是将这样的优化限制在逻辑综合的范围之内。 也就是说，我们提出了一种积极的优化方法，在技术独立合成中识别电路结构，并产生更可预测的实现，从而提供更好的可路由性和产量。

公开(公告)号：US07308593B2

公开(公告)日：2007-12-11

申请号：US11376544

申请日：2006-03-14

申请人： Hans M. Jacobson ,  Prabhakar N. Kudva ,  Pradip Bose ,  Peter W. Cook ,  Stanley E. Schuster

发明人： Hans M. Jacobson ,  Prabhakar N. Kudva ,  Pradip Bose ,  Peter W. Cook ,  Stanley E. Schuster

IPC分类号： H04L5/00 ,  G06F9/30

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3275 ,  G06F9/3869 ,  G06F9/3871 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/14

摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

摘要翻译： 一种包括管道的集成电路和操作管道的方法。 流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。 对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。 用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

公开(公告)号：US07100144B2

公开(公告)日：2006-08-29

申请号：US10731840

申请日：2003-12-09

申请人： Hans M. Jacobson ,  Prabhakar N. Kudva ,  Leon J. Sigal

发明人： Hans M. Jacobson ,  Prabhakar N. Kudva ,  Leon J. Sigal

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology and the leakage sensitivities for each of the topologies is calculated. The system is then configured to synthesize a new circuit model by selecting one or more of the topologies based on its leakage sensitivities, wherein the new circuit model has reduced current leakage.

摘要翻译： 一种用于在合成期间最小化泄漏功率的拓扑选择的系统，其中所述系统被配置为接收具有一个或多个电路门的电路模型。 该系统还被配置为接收具有一个或多个逻辑门的库，其中每个逻辑门具有拓扑，并且计算每个拓扑的泄漏灵敏度。 然后，该系统被配置为通过基于其泄漏灵敏度选择一个或多个拓扑来合成新的电路模型，其中新的电路模型具有减少的电流泄漏。