公开(公告)号：US07164598B2

公开(公告)日：2007-01-16

申请号：US11201495

申请日：2005-08-11

申请人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/00 ,  G11C11/15

CPC分类号： G11C11/16

摘要： Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

摘要翻译： 提供了用于操作包括在衬底上具有磁性隧道结结构的存储单元的磁性随机存取存储器件的方法。 特别地，可以通过磁性隧道结结构提供写入电流脉冲，并且可以通过磁性隧道结结构提供写入磁场脉冲。 此外，写入磁场脉冲的至少一部分可以相对于写入电流脉冲的至少一部分在时间上重叠，并且写入电流脉冲的至少一部分和/或至少一部分 写入磁场脉冲可能在时间上相对于另一个不重叠。 还讨论了相关设备。

公开(公告)号：US20060034117A1

公开(公告)日：2006-02-16

申请号：US11201495

申请日：2005-08-11

申请人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Ki-Nam Kim ,  Hong-Sik Jeong ,  Gi-Tae Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： Methods are provided for operating a magnetic random access memory device including a memory cell having a magnetic tunnel junction structure on a substrate. In particular, a writing current pulse may be provided through the magnetic tunnel junction structure, and a writing magnetic field pulse may be provided through the magnetic tunnel junction structure. In addition, at least a portion of the writing magnetic field pulse may be overlapping in time with respect to at least a portion of the writing current pulse, and at least a portion of the writing current pulse and/or at least a portion of the writing magnetic field pulse may be non-overlapping in time with respect to the other. Related devices are also discussed.

摘要翻译： 提供了用于操作包括在衬底上具有磁性隧道结结构的存储单元的磁性随机存取存储器件的方法。 特别地，可以通过磁性隧道结结构提供写入电流脉冲，并且可以通过磁性隧道结结构提供写入磁场脉冲。 此外，写入磁场脉冲的至少一部分可以相对于写入电流脉冲的至少一部分在时间上重叠，并且写入电流脉冲的至少一部分和/或至少一部分 写入磁场脉冲可能在时间上相对于另一个不重叠。 还讨论了相关设备。

公开(公告)号：US07569401B2

公开(公告)日：2009-08-04

申请号：US12048082

申请日：2008-03-13

申请人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

发明人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

IPC分类号： H01L21/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12

摘要： Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

摘要翻译： 磁性RAM单元具有由包覆层包围的分割的子数字线，并且提供其制造方法。 磁性RAM单元包括在半导体衬底上形成的第一和第二子数字线。 只有第一子数字线的底表面和外侧壁被第一覆层图案覆盖。 此外，仅第二子数字线的底表面和外侧壁被第二包层图案覆盖。 第一子数字线的外侧壁位于远离第二子数字线的位置，第二子数字线的外侧壁位于第一子数字线的远侧。 还提供了制造磁性RAM单元的方法。

公开(公告)号：US20080160643A1

公开(公告)日：2008-07-03

申请号：US12048082

申请日：2008-03-13

申请人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

发明人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

IPC分类号： H01L43/12

CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12

摘要： Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

摘要翻译： 磁性RAM单元具有由包覆层包围的分割的子数字线，并且提供其制造方法。 磁性RAM单元包括在半导体衬底上形成的第一和第二子数字线。 只有第一子数字线的底表面和外侧壁被第一覆层图案覆盖。 此外，仅第二子数字线的底表面和外侧壁被第二包层图案覆盖。 第一子数字线的外侧壁位于远离第二子数字线的位置，第二子数字线的外侧壁位于第一子数字线的远侧。 还提供了制造磁性RAM单元的方法。

公开(公告)号：US20050205952A1

公开(公告)日：2005-09-22

申请号：US11077669

申请日：2005-03-11

申请人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

发明人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

IPC分类号： H01L21/00 ,  H01L21/8246 ,  H01L27/22 ,  H01L29/82 ,  H01L43/08 ,  H01L43/12

CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12

摘要： Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

摘要翻译： 磁性RAM单元具有由包覆层包围的分割的子数字线，并且提供其制造方法。 磁性RAM单元包括在半导体衬底上形成的第一和第二子数字线。 只有第一子数字线的底表面和外侧壁被第一覆层图案覆盖。 此外，仅第二子数字线的底表面和外侧壁被第二包层图案覆盖。 第一子数字线的外侧壁位于远离第二子数字线的位置，第二子数字线的外侧壁位于第一子数字线的远侧。 还提供了制造磁性RAM单元的方法。

公开(公告)号：US08120005B2

公开(公告)日：2012-02-21

申请号：US12544104

申请日：2009-08-19

申请人： Jae-Hyun Park ,  Jae-Hee Oh ,  Se-Ho Lee ,  Won-Cheol Jeong

发明人： Jae-Hyun Park ,  Jae-Hee Oh ,  Se-Ho Lee ,  Won-Cheol Jeong

IPC分类号： H01L45/00

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1666

摘要： In an embodiment, a phase change memory device includes a semiconductor substrate of a first conductivity type and a first interlayer insulating layer disposed on the semiconductor substrate. A hole penetrates the first interlayer insulating layer. A first and a second semiconductor pattern are sequentially stacked in a lower region of the hole. A cell electrode is provided on the second semiconductor pattern. The cell electrode has a lower surface than a top surface of the first interlayer insulating layer. A confined phase change material pattern fills the hole on the cell electrode. An upper electrode is disposed on the phase change material pattern. The phase change material pattern in the hole is self-aligned with the first and second semiconductor patterns by the hole. A method of fabricating the phase change memory device is also provided.

摘要翻译： 在一个实施例中，相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的第一层间绝缘层。 一个孔穿透第一层间绝缘层。 第一和第二半导体图案顺序地堆叠在孔的下部区域中。 电池电极设置在第二半导体图案上。 电池电极具有比第一层间绝缘层的顶表面更低的表面。 限制的相变材料图案填充电池电极上的孔。 上电极设置在相变材料图案上。 孔中的相变材料图案通过孔与第一和第二半导体图案自对准。 还提供了制造相变存储器件的方法。

公开(公告)号：US07671395B2

公开(公告)日：2010-03-02

申请号：US12240267

申请日：2008-09-29

申请人： Jae-Hyun Park ,  Jae-Hee Oh ,  Se-Ho Lee ,  Won-Cheol Jeong

发明人： Jae-Hyun Park ,  Jae-Hee Oh ,  Se-Ho Lee ,  Won-Cheol Jeong

IPC分类号： H01L27/108

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.

摘要翻译： 在其中提供具有垂直二极管的集成电路器件。 这些器件包括集成电路衬底和集成电路衬底上的绝缘层。 接触孔穿透绝缘层。 垂直二极管位于接触孔的下部区域中，接触孔中的底部电极在垂直二极管的顶面具有底面。 底部电极与垂直二极管自对准。 底部电极的顶表面积小于接触孔的水平截面面积。 还提供了形成集成电路器件和相变存储器单元的方法。

公开(公告)号：US07577016B2

公开(公告)日：2009-08-18

申请号：US11094948

申请日：2005-03-31

申请人： Won-Cheol Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673

摘要： Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers.

摘要翻译： 提供了包括多个主位线和多个参考位线的双电池型半导体存储器件。 每个参考位线对应于主位线中的相应位线以形成多个位线对。 提供多个读出放大器，其电连接到多个位线对中的相应一个。 多个主位线或多个参考位线中的至少一个被插入在每个位线对的主位线和对应的参考位线之间。 至少一些主位线可以在包含多个读出放大器的半导体存储器件的读出放大器区域中交叉相应的参考位线。

公开(公告)号：US20090026439A1

公开(公告)日：2009-01-29

申请号：US12240267

申请日：2008-09-29

申请人： Jae-Hyun Park ,  Jae-Hee Oh ,  Se-Ho Lee ,  Won-Cheol Jeong

发明人： Jae-Hyun Park ,  Jae-Hee Oh ,  Se-Ho Lee ,  Won-Cheol Jeong

IPC分类号： H01L47/00

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： Integrated circuit devices are provide having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.

摘要翻译： 在其中提供具有垂直二极管的集成电路器件。 这些器件包括集成电路衬底和集成电路衬底上的绝缘层。 接触孔穿透绝缘层。 垂直二极管位于接触孔的下部区域中，接触孔中的底部电极在垂直二极管的顶面具有底面。 底部电极与垂直二极管自对准。 底部电极的顶表面积小于接触孔的水平截面面积。 还提供了形成集成电路器件和相变存储器单元的方法。

公开(公告)号：US20060011958A1

公开(公告)日：2006-01-19

申请号：US11092362

申请日：2005-03-29

申请人： Won-Cheol Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Jae-Hyun Park

IPC分类号： H01L29/94

CPC分类号： H01L43/08 ,  G11C11/16 ,  H01L27/222

摘要： A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line. In addition, a second magnetic layer may be provided on the bit line.

摘要翻译： 磁性随机存取存储器（MRAM）器件可以包括衬底，衬底上的第一磁性层以及第一磁性层上的数字线。 可以在数字线附近提供磁性隧道结结构，并且可以在磁性隧道结结构上提供位线，使得磁性隧道结结构位于位线和数字线之间。 此外，可以在位线上设置第二磁性层。