公开(公告)号：US20140061772A1

公开(公告)日：2014-03-06

申请号：US14076806

申请日：2013-11-11

申请人： Won-Cheol Jeong ,  Su-Jin Ahn ,  Yoon-Moon Park

发明人： Won-Cheol Jeong ,  Su-Jin Ahn ,  Yoon-Moon Park

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66833 ,  H01L29/792

摘要： Nonvolatile memory devices are provided. Devices include active regions that may be defined by device isolation layers formed on a semiconductor substrate and extend in a first direction. Devices may also include word lines that may cross over the active regions and extend in a second direction intersecting the first direction. The active regions have a first pitch and the word lines have a second pitch that is greater than the first pitch.

摘要翻译： 提供非易失性存储器件。 器件包括可以由形成在半导体衬底上并沿第一方向延伸的器件隔离层限定的有源区。 设备还可以包括字线，其可以跨越有效区域并且沿与第一方向相交的第二方向延伸。 有源区具有第一间距，并且字线具有大于第一间距的第二间距。

公开(公告)号：US08422275B2

公开(公告)日：2013-04-16

申请号：US12372492

申请日：2009-02-17

申请人： In-jun Hwang ,  Tae-wan Kim ,  Won-cheol Jeong

发明人： In-jun Hwang ,  Tae-wan Kim ,  Won-cheol Jeong

IPC分类号： G11C11/00

CPC分类号： G11C11/15

摘要： An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction. Methods of operating and manufacturing these magnetic random access memories are also disclosed.

公开(公告)号：US20090268515A1

公开(公告)日：2009-10-29

申请号：US12498597

申请日：2009-07-07

申请人： Won-Cheol Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/14 ,  G11C7/02

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673

摘要： Twin cell type semiconductor memory devices are provided that include a plurality of main bit lines and a plurality of reference bit lines. Each of the reference bit lines correspond to respective ones of the main bit lines to form a plurality of bit line pairs. A plurality of sense amplifiers are provided that are electrically connected to a respective one of the plurality of bit line pairs. At least one of the plurality of main bit lines or the plurality of reference bit lines is interposed between the main bit line and the corresponding reference bit line of each bit line pair. At least some of the main bit lines may cross respective ones of the reference bit lines in a sense amplifier region of the semiconductor memory device that contains the plurality of sense amplifiers.

摘要翻译： 提供了包括多个主位线和多个参考位线的双电池型半导体存储器件。 每个参考位线对应于主位线中的相应位线以形成多个位线对。 提供多个读出放大器，其电连接到多个位线对中的相应一个。 多个主位线或多个参考位线中的至少一个被插入在每个位线对的主位线和对应的参考位线之间。 至少一些主位线可以在包含多个读出放大器的半导体存储器件的读出放大器区域中交叉相应的参考位线。

公开(公告)号：US20090236651A1

公开(公告)日：2009-09-24

申请号：US12463545

申请日：2009-05-11

申请人： Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

发明人： Dong Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC分类号： H01L27/105 ,  H01L29/788

CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

公开(公告)号：US07589994B2

公开(公告)日：2009-09-15

申请号：US12171893

申请日：2008-07-11

申请人： Won-Cheol Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/00

CPC分类号： H01L43/08 ,  G11C11/16 ,  H01L27/222

摘要： A magnetic random access memory (MRAM) device may include a substrate, a first magnetic layer on the substrate, and a digit line on the first magnetic layer. A magnetic tunnel junction structure may be provided adjacent the digit line, and a bit line may be provided on the magnetic tunnel junction structure such that the magnetic tunnel junction structure is between the bit line and the digit line. In addition, a second magnetic layer may be provided on the bit line.

摘要翻译： 磁性随机存取存储器（MRAM）器件可以包括衬底，衬底上的第一磁性层和第一磁性层上的数字线。 可以在数字线附近提供磁性隧道结结构，并且可以在磁性隧道结结构上提供位线，使得磁性隧道结结构位于位线和数字线之间。 此外，可以在位线上设置第二磁性层。

公开(公告)号：US07569401B2

公开(公告)日：2009-08-04

申请号：US12048082

申请日：2008-03-13

申请人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

发明人： Jae-Hyun Park ,  Hyeong-Jun Kim ,  Won-Cheol Jeong ,  Chang-Wook Jeong ,  Hong-sik Jeong ,  Gi-Tae Jeong

IPC分类号： H01L21/00

CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12

摘要： Magnetic RAM cells have split sub-digit lines surrounded by cladding layers and methods of fabricating the same are provided. The magnetic RAM cells include first and second sub-digit lines formed over a semiconductor substrate. Only a bottom surface and an outer sidewall of the first sub-digit line are covered with a first cladding layer pattern. In addition, only a bottom surface and an outer sidewall of the second sub-digit line are covered with a second cladding layer pattern. The outer sidewall of the first sub-digit line is located distal from the second sub-digit line and the outer sidewall of the second sub-digit line is located distal the first sub-digit line. Methods of fabricating the magnetic RAM cells are also provided.

摘要翻译： 磁性RAM单元具有由包覆层包围的分割的子数字线，并且提供其制造方法。 磁性RAM单元包括在半导体衬底上形成的第一和第二子数字线。 只有第一子数字线的底表面和外侧壁被第一覆层图案覆盖。 此外，仅第二子数字线的底表面和外侧壁被第二包层图案覆盖。 第一子数字线的外侧壁位于远离第二子数字线的位置，第二子数字线的外侧壁位于第一子数字线的远侧。 还提供了制造磁性RAM单元的方法。

公开(公告)号：US20090159962A1

公开(公告)日：2009-06-25

申请号：US12338308

申请日：2008-12-18

申请人： Hyun Suk Kim ,  Sun-II Shim ,  Chang-Seok Kang ,  Won-Cheol Jeong ,  Jung-Dal Choi ,  Jae-Kwan Park ,  Seung-Hyun Lim ,  Sun-Jung Kim

发明人： Hyun Suk Kim ,  Sun-II Shim ,  Chang-Seok Kang ,  Won-Cheol Jeong ,  Jung-Dal Choi ,  Jae-Kwan Park ,  Seung-Hyun Lim ,  Sun-Jung Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

摘要： Non-volatile memory devices are provided including a control gate electrode on a substrate; a charge storage insulation layer between the control gate electrode and the substrate; a tunnel insulation layer between the charge storage insulation layer and the substrate; a blocking insulation layer between the charge storage insulation layer and the control gate electrode; and a material layer between the tunnel insulation layer and the blocking insulation layer, the material layer having an energy level constituting a bottom of a potential well.

摘要翻译： 提供了非易失性存储器件，其包括在衬底上的控制栅电极; 在控制栅电极和衬底之间的电荷存储绝缘层; 在电荷存储绝缘层和衬底之间的隧道绝缘层; 电荷存储绝缘层和控制栅电极之间的阻挡绝缘层; 以及隧道绝缘层和阻挡绝缘层之间的材料层，材料层具有构成势阱底部的能级。

公开(公告)号：US07544565B2

公开(公告)日：2009-06-09

申请号：US11642198

申请日：2006-12-20

申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

IPC分类号： H01L21/8247

CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。

公开(公告)号：US07442602B2

公开(公告)日：2008-10-28

申请号：US11389996

申请日：2006-03-27

申请人： Jae-Hyun Park ,  Jae-Hee Oh ,  Se-Ho Lee ,  Won-Cheol Jeong

发明人： Jae-Hyun Park ,  Jae-Hee Oh ,  Se-Ho Lee ,  Won-Cheol Jeong

IPC分类号： H01L21/8234

CPC分类号： H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.

摘要翻译： 在其中提供具有垂直二极管的集成电路器件。 这些器件包括集成电路衬底和集成电路衬底上的绝缘层。 接触孔穿透绝缘层。 垂直二极管位于接触孔的下部区域中，接触孔中的底部电极在垂直二极管的顶面具有底面。 底部电极与垂直二极管自对准。 底部电极的顶表面积小于接触孔的水平截面面积。 还提供了形成集成电路器件和相变存储器单元的方法。

公开(公告)号：US07372722B2

公开(公告)日：2008-05-13

申请号：US11263521

申请日：2005-10-31

申请人： Won-Cheol Jeong ,  Jae-Hyun Park

发明人： Won-Cheol Jeong ,  Jae-Hyun Park

IPC分类号： G11C11/00 ,  G11C11/34

CPC分类号： G11C11/15

摘要： Methods may be provided for operating a magnetic random access memory (MRAM device including a magnetic tunnel junction structure and a heat generating layer. More particularly, a write current may be provided through the magnetic tunnel junction structure and through the heat generating layer, and the write current may have a magnitude sufficient to change a program state of the magnetic tunnel junction structure. Related devices are also discussed.

摘要翻译： 可以提供用于操作磁性随机存取存储器（包括磁性隧道结结构和发热层的MRAM器件）的方法，更具体地说，可以通过磁性隧道结结构和通过发热层提供写入电流， 写入电流可能具有足以改变磁性隧道结结构的编程状态的量值，还讨论了相关器件。