公开(公告)号：US06710465B2

公开(公告)日：2004-03-23

申请号：US10345161

申请日：2003-01-16

申请人： Seungheon Song ,  Woosik Kim ,  Hokyu Kang

发明人： Seungheon Song ,  Woosik Kim ,  Hokyu Kang

IPC分类号： H01L2711

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  Y10S257/904

摘要： A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

摘要翻译： 具有4F 2单位单元面积的可扩展双晶体管存储器（STTM）单元阵列，其中F是最小特征尺寸。 数据线和位线沿着Y轴方向交替并彼此相邻，并且字线沿着X轴方向布置。 每个STTM单元由在半导体衬底的表面处的浮置栅极MOS感测晶体管组成，在感测晶体管顶部具有垂直双侧壁栅极多隧道结屏障编程MOS晶体管。 数据线连接编程晶体管的所有源极区域，并且位线沿列方向连接感测晶体管的所有源极/漏极区域。 字线将编程晶体管的所有双侧壁栅极区域沿行方向连接。 本发明还涉及列寻址电路以及该电路的驱动方法。

公开(公告)号：US06528896B2

公开(公告)日：2003-03-04

申请号：US09884911

申请日：2001-06-21

申请人： Seungheon Song ,  Woosik Kim ,  Hokyu Kang

发明人： Seungheon Song ,  Woosik Kim ,  Hokyu Kang

IPC分类号： H01L2711

CPC分类号： G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  Y10S257/904

摘要： A Scalable Two-Transistor Memory (STTM) cell array having a 4F2 unit cell area, where F is the minimum feature size. The data lines and the bit lines alternate and are adjacent to each other along the Y-axis direction, and the word lines are laid out along the X-axis direction. Each STTM cell consists of a floating gate MOS sensing transistor at the surface of a semiconductor substrate, with a vertical double sidewall gate multiple tunnel junction barrier programming MOS transistor on top of the sensing transistor. A data line connects all source regions of the programming transistors and a bit line connects all the source/drain regions of the sensing transistors in a column direction. A word line connects all double sidewall gate regions of programming transistors in a row direction. This invention also deals with a column addressing circuit as well as the driving method for the circuit.

摘要翻译： 具有4F2单位区域的可扩展双晶体管存储器（STTM）单元阵列，其中F是最小特征尺寸。 数据线和位线沿着Y轴方向交替并彼此相邻，并且字线沿着X轴方向布置。 每个STTM单元由在半导体衬底的表面处的浮置栅极MOS感测晶体管组成，在感测晶体管顶部具有垂直双侧壁栅极多隧道结屏障编程MOS晶体管。 数据线连接编程晶体管的所有源极区域，并且位线沿列方向连接感测晶体管的所有源极/漏极区域。 字线将编程晶体管的所有双侧壁栅极区域沿行方向连接。 本发明还涉及列寻址电路以及该电路的驱动方法。

公开(公告)号：US06475857B1

公开(公告)日：2002-11-05

申请号：US09884912

申请日：2001-06-21

申请人： Woosik Kim ,  Seungheon Song ,  Hokyu Kang

发明人： Woosik Kim ,  Seungheon Song ,  Hokyu Kang

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： A method of fabricating a multiple tunnel junction Scalable Two-Transistor Memory (STTM) cell array with a unit cell area as low as 4F2, F representing the minimum feature dimension, which usually is the width and also the spacing of the data lines or the write (or word or control gate) lines, wherein process sequence and conditions are designed to offer wide flexibility in material choices and layer thickness at different regions of the STTM cell with surface planarity maintained at several stages of the manufacturing sequence. The processing of memory cell devices is made compatible with peripheral CMOS devices so that the devices in both areas can be made simultaneously, thereby decreasing the total number of processing steps. Insulator filled trenches around the device regions, source/drain and the gate regions of the peripheral devices are formed simultaneously with the corresponding regions of the memory cell devices.

摘要翻译： 一种制造具有低至4F2的单元单元面积的多隧道结可伸缩双晶体管存储器（STTM）单元阵列的方法，F表示最小特征尺寸，其通常是数据线的宽度和间距 写（或字或控制门）线，其中工艺顺序和条件被设计为在STTM单元的不同区域处提供在材料选择和层厚度方面的广泛的灵活性，并且在制造顺序的几个阶段保持表面平面度。 存储单元设备的处理与外围CMOS器件兼容，使得两个区域中的器件可以同时进行，从而减少处理步骤的总数。 绝缘体在器件区域周围填充沟槽，外围器件的源极/漏极和栅极区域与存储器单元器件的相应区域同时形成。

公开(公告)号：US20080246148A1

公开(公告)日：2008-10-09

申请号：US11972192

申请日：2008-01-10

申请人： Seokjun Won ,  Hokyu Kang

发明人： Seokjun Won ,  Hokyu Kang

IPC分类号： H01L23/52

CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit devices include electrically conductive interconnects containing carbon nanotubes. An electrical interconnect includes a first metal region. A first electrically conductive barrier layer is provided on an upper surface of the first metal region and a second metal region is provided on the first electrically conductive barrier layer. The first electrically conductive barrier layer includes a material that inhibits out-diffusion of the first metal from the first metal region and the second metal region includes a catalytic metal therein. An electrically insulating layer having an opening therein is provided on the second metal region. A plurality of carbon nanotubes are provided as a vertical electrical interconnect in the opening.

摘要翻译： 集成电路器件包括含有碳纳米管的导电互连。 电互连包括第一金属区域。 第一导电阻挡层设置在第一金属区域的上表面上，第二金属区域设置在第一导电阻挡层上。 第一导电阻挡层包括抑制第一金属从第一金属区域的扩散扩散的材料，第二金属区域包括催化金属。 其中具有开口的电绝缘层设置在第二金属区域上。 在开口中设置多个碳纳米管作为垂直电互连。