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    FREQUENCY MULTIPLICATION USING SELF-MIXING
    2.
    发明申请
    FREQUENCY MULTIPLICATION USING SELF-MIXING 有权
    使用自混合的频率乘法

    公开(公告)号：US20120276857A1

    公开(公告)日：2012-11-01

    申请号：US13449468

    申请日：2012-04-18

    申请人： Xiang Gao ,  Chi-Hung Lin ,  Li Lin

    发明人： Xiang Gao ,  Chi-Hung Lin ,  Li Lin

    IPC分类号： H04B1/38 ,  H03K21/00 ,  H03B19/14

    CPC分类号： H03B19/00

    摘要： Frequency multipliers having corresponding methods and multifunction radios comprise: N multipliers, wherein N is an integer greater than one; wherein the multipliers are connected in series such that each of the multipliers, except for a first one of the multipliers, is configured to mix a periodic input signal with an output of another respective one of the multipliers; wherein the first one of the multipliers is configured to mix the periodic input signal with the periodic input signal.

    摘要翻译： 具有相应方法和多功能无线电的频率乘法器包括：N个乘法器，其中N是大于1的整数; 其中所述乘法器串联连接，使得除所述乘法器中的第一乘法器之外的每个乘法器被配置为将周期性输入信号与所述乘法器中的另一相应乘法器的输出混合; 其中所述乘法器中的所述第一乘法器被配置为将所述周期性输入信号与所述周期性输入信号混合。

    Frequency multiplication using self-mixing
    3.
    发明授权
    Frequency multiplication using self-mixing 有权
    使用自动混频进行倍频

    公开(公告)号：US08838053B2

    公开(公告)日：2014-09-16

    申请号：US13449468

    申请日：2012-04-18

    申请人： Li Lin ,  Xiang Gao ,  Chi-Hung Lin

    发明人： Li Lin ,  Xiang Gao ,  Chi-Hung Lin

    IPC分类号： H04B1/18 ,  H03B19/00

    CPC分类号： H03B19/00

    摘要： Frequency multipliers having corresponding methods and multifunction radios comprise: N multipliers, wherein N is an integer greater than one; wherein the multipliers are connected in series such that each of the multipliers, except for a first one of the multipliers, is configured to mix a periodic input signal with an output of another respective one of the multipliers; wherein the first one of the multipliers is configured to mix the periodic input signal with the periodic input signal.

    摘要翻译： 具有相应方法和多功能无线电的频率乘法器包括：N个乘法器，其中N是大于1的整数; 其中所述乘法器串联连接，使得除所述乘法器中的第一乘法器之外的每个乘法器被配置为将周期性输入信号与所述乘法器中的另一相应乘法器的输出混合; 其中所述乘法器中的所述第一乘法器被配置为将所述周期性输入信号与所述周期性输入信号混合。

    Transceiver front-end
    4.
    发明授权
    Transceiver front-end 有权
    收发器前端

    公开(公告)号：US08081932B2

    公开(公告)日：2011-12-20

    申请号：US11400288

    申请日：2006-04-10

    申请人： Jan Roelof Westra ,  Rudy J. van de Plassche ,  Chi-Hung Lin

    发明人： Jan Roelof Westra ,  Rudy J. van de Plassche ,  Chi-Hung Lin

    IPC分类号： H04B1/44

    CPC分类号： H04B1/583

    摘要： A transceiver front-end provides an interface between a transmission medium and transmitter, and between a transmission medium and receiver. The transceiver front-end includes a hybrid circuit, a high-pass filter, and a gain stage, that permits the reduction or the complete elimination of buffer amplifiers. Buffer amplifiers can be eliminated because the hybrid circuit and/or the high-pass filter are adapted so that they can be directly connected to each other, without a loss in circuit performance. Furthermore, the high-pass filter and/or the gain stage are also adapted so they can be directly connected. As such, the transceiver front-end can be constructed using all passive components, reducing or eliminating excess heat generation.

    摘要翻译： 收发器前端提供传输介质和发射器之间以及传输介质和接收器之间的接口。 收发器前端包括混合电路，高通滤波器和增益级，允许减少或完全消除缓冲放大器。 可以消除缓冲放大器，因为混合电路和/或高通滤波器被适配成使得它们可以彼此直接连接，而不会损失电路性能。 此外，高通滤波器和/或增益级也适于直接连接。 因此，收发器前端可以使用所有无源组件构建，从而减少或消除多余的发热。

    Computer having function for displaying status of operation and floppy module
    5.
    发明授权
    Computer having function for displaying status of operation and floppy module 有权
    具有显示操作状态和软盘模块功能的计算机

    公开(公告)号：US08055811B2

    公开(公告)日：2011-11-08

    申请号：US12564054

    申请日：2009-09-22

    申请人： Hsi-Jung Tsai ,  Chi-Hung Lin ,  Shih-Hao Yeh

    发明人： Hsi-Jung Tsai ,  Chi-Hung Lin ,  Shih-Hao Yeh

    IPC分类号： G06F3/00

    CPC分类号： G11B17/0436

    摘要： A floppy module includes a floppy disk controller (FDC), a control circuit, and a display. The FDC has a first control terminal, a second control terminal, and a plurality of third control terminals. Wherein, the first control terminal and the second control terminal may respectively output a first control signal and a second control signal, and the first and second control signals having the same statuses are used for controlling a floppy disk. The display has a fourth control terminal and a plurality of data terminals respectively coupled to a portion of the third control terminals. Additionally, the control circuit may use the first control signal to replace the second control signal for controlling the floppy disk, and transmit the second control signal to the fourth control terminal such that a status information is shown on the display as the floppy disk being idle.

    摘要翻译： 软盘模块包括软盘控制器（FDC），控制电路和显示器。 FDC具有第一控制终端，第二控制终端和多个第三控制终端。 其中，第一控制终端和第二控制终端可以分别输出第一控制信号和第二控制信号，并且具有相同状态的第一和第二控制信号用于控制软盘。 显示器具有分别耦合到第三控制端子的一部分的第四控制端子和多个数据端子。 此外，控制电路可以使用第一控制信号来替换用于控制软盘的第二控制信号，并且将第二控制信号发送到第四控制终端，使得在软盘空闲时在显示器上显示状态信息 。

    Digital to analog converter with reduced ringing
    7.
    发明授权
    Digital to analog converter with reduced ringing 失效
    数模转换器减少振铃

    公开(公告)号：US07317414B2

    公开(公告)日：2008-01-08

    申请号：US11698954

    申请日：2007-01-29

    申请人： Klaas Bult ,  Chi-Hung Lin

    发明人： Klaas Bult ,  Chi-Hung Lin

    IPC分类号： H03M1/66

    CPC分类号： H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

    摘要： Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

    摘要翻译： 二进制指示被转换为模拟表示，在连续的二进制指示之间的转换和每个二进制指示期间的周期中显着地减少振铃。 二进制指示以行和列矩阵布置以提供温度计代码。 转换器的每个级包括一个解码器和锁存器，所述解码器和锁存器布置成使得解码器输入在锁存器被时钟脉冲设置之前稳定。 这些阶段在互补CMOS中实现。 互补晶体管是偏置的，因此该对的一个晶体管被驱动到轨道，而另一个晶体管则浮动。 虚拟CMOS晶体管用于平衡解码器路径中的晶体管数量。

    Single-ended-to-differential converter with common-mode voltage control
    10.
    发明授权
    Single-ended-to-differential converter with common-mode voltage control 有权
    具有共模电压控制的单端到差分转换器

    公开(公告)号：US06873210B2

    公开(公告)日：2005-03-29

    申请号：US10791878

    申请日：2004-03-04

    申请人： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

    发明人： Jan Mulder ,  Marcel Lugthart ,  Chi-Hung Lin

    IPC分类号： H03H11/32 ,  H03F3/45

    CPC分类号： H03H11/32

    摘要： Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

    摘要翻译： 提供了在提供共模电压控制的同时执行单端到差分转换的电路。 电路包括将单端信号转换为差分信号的转换器和适于接收差分信号的稳定电路。 稳定电路包括被配置为感测差分信号的共模电压电平的传感器和具有耦合到转换器的输出端口的比较器。 比较器被配置为将差分信号共模电压电平与参考信号共模电压电平进行比较，并且基于该比较产生调整信号。 调整信号经由输出端口被施加到转换器，并且可操作地调整差分信号的后续共模电压电平。