公开(公告)号：US20050260808A1

公开(公告)日：2005-11-24

申请号：US10851830

申请日：2004-05-21

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining Yang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining Yang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

摘要翻译： 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

公开(公告)号：US07002209B2

公开(公告)日：2006-02-21

申请号：US10851830

申请日：2004-05-21

申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

摘要翻译： 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

公开(公告)号：US20070096223A1

公开(公告)日：2007-05-03

申请号：US11163686

申请日：2005-10-27

申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

IPC分类号： H01L27/12

CPC分类号： H01L29/1083 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/31675 ,  H01L29/7833 ,  H01L29/7846

摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A first dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region, such as a northwest portion of the active semiconductor region. A second dielectric stressor element having a horizontally extending upper surface extends below a second portion of the active semiconductor region, such as a southeast portion of the active semiconductor region. Each of the first and second dielectric stressor elements shares an edge with the active semiconductor region, the edges extending in directions away from the upper surface.

摘要翻译： 提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 具有水平延伸的上表面的第一介电应激元件在有源半导体区域的一部分的下方延伸，例如有源半导体区域的西北部分。 具有水平延伸的上表面的第二介电应激元件在有源半导体区域的第二部分的下方延伸，例如有源半导体区域的东南部分。 第一和第二介电应力元件中的每一个与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。

公开(公告)号：US20070114632A1

公开(公告)日：2007-05-24

申请号：US11164373

申请日：2005-11-21

申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

IPC分类号： H01L29/00 ,  H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A buried dielectric stressor element has a horizontally extending upper surface at a first depth below a major surface of a portion of the active semiconductor region, such as an east portion of the active semiconductor region. A surface dielectric stressor element is disposed laterally adjacent to the active semiconductor region at the major surface of the active semiconductor region. The surface dielectric stressor element extends from the major surface to a second depth not substantially greater than the first depth. The stresses applied by the buried and surface dielectric stressor elements cooperate together to apply a shear stress to the channel region of the FET.

摘要翻译： 提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 掩埋介质应力元件在有源半导体区域的一部分的主表面下方的第一深度（例如有源半导体区域的东部）处具有水平延伸的上表面。 在有源半导体区域的主表面处，表面介电应力元件横向邻近有源半导体区域设置。 表面介电应力元件从主表面延伸到不大于第一深度的第二深度。 由埋层和表面介电应力元件施加的应力协同工作，对FET的沟道区施加剪切应力。

公开(公告)号：US20070122956A1

公开(公告)日：2007-05-31

申请号：US11164632

申请日：2005-11-30

申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

IPC分类号： H01L21/8234 ,  H01L31/00 ,  H01L21/336

CPC分类号： H01L29/7849 ,  H01L21/26513 ,  H01L21/31675 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654

摘要： A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element includes a region of collapsed oxide which fully contacts the bottom surface of the active semiconductor region such that it has an area coextensive with an area of the bottom surface. Bird's beak oxide regions at edges of the dielectric stressor element apply an upward force at edges of the dielectric stressor element to impart a compressive stress to the channel region of the PFET.

摘要翻译： 压缩应力通过结构施加到PFET的沟道区域，其包括完全位于其中设置有PFET的源极，漏极和沟道区域的有源半导体区域的底表面的离散介电应激元件。 特别地，介电应力元件包括与活性半导体区域的底表面完全接触的塌陷氧化物区域，使得其具有与底表面的区域共同延伸的区域。 电介质应力元件边缘处的鸟喙氧化物区域在介质应力元件的边缘施加向上的力，以向PFET的沟道区域施加压应力。

公开(公告)号：US20070096215A1

公开(公告)日：2007-05-03

申请号：US11163683

申请日：2005-10-27

申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823481 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/0653 ,  H01L29/7846

摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region. The dielectric stressor element shares an edge with the active semiconductor region, the edge extending in a direction away from the upper surface. In particular structures, two or more dielectric stressor elements are provided at locations opposite from each other in the longitudinal and/or transverse directions of the FET.

摘要翻译： 提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 具有水平延伸的上表面的介电应激元件在有源半导体区域的一部分的下方延伸。 电介质应力元件与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。 在特定结构中，在FET的纵向和/或横向方向上彼此相对的位置处提供两个或更多个介电应激元件。

公开(公告)号：US20070069300A1

公开(公告)日：2007-03-29

申请号：US11162959

申请日：2005-09-29

申请人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Brian Greene ,  Jack Mandelman ,  Kern Rim

发明人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Brian Greene ,  Jack Mandelman ,  Kern Rim

IPC分类号： H01L29/94

CPC分类号： H01L21/2652 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 超薄（UT）绝缘体上半导体通道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。 源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 第一BOX区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。 在UT通道区域下面的第二BOX区域的上部自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于 第二个深度。

公开(公告)号：US20070249126A1

公开(公告)日：2007-10-25

申请号：US11308685

申请日：2006-04-21

申请人： Dureseti Chidambarrao ,  Brian Greene ,  John Ellis-Monaghan

发明人： Dureseti Chidambarrao ,  Brian Greene ,  John Ellis-Monaghan

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/823814

摘要： A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant concentration at an interface of the SOI layer to the buried dielectric layer. and (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to the poly gate, wherein a maximum depth of the first implanting is greater than a maximum depth of the second implanting.

摘要翻译： 提供一种用于制造晶体管结构的结构和方法。 该方法包括以下步骤：（a）提供包括绝缘体上半导体（“SOI”）层的衬底，该衬底通过掩埋电介质层与衬底的主体区域分离。 （b）首先注入SOI层以在SOI层与掩埋介电层的界面处实现预定的掺杂剂浓度。 以及（c）第二次注入所述SOI层以在多晶半导体栅极导体（“多晶硅”）中以及在与所述多晶硅栅极相邻设置的源极和漏极区域中实现预定的掺杂剂浓度，其中所述第一注入的最大深度大于 第二次植入的最大深度。

公开(公告)号：US20070018205A1

公开(公告)日：2007-01-25

申请号：US11161066

申请日：2005-07-21

申请人： Dureseti Chidambarrao ,  Brian Greene

发明人： Dureseti Chidambarrao ,  Brian Greene

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area and the trench isolation region, without requiring a trench isolation pulldown, thereby eliminating the problems of silicide to source/drain shorts and contact issues. At the same time, the method of the present invention provides a structure that allows for a facet to form at the spacer edge, retaining the Miller capacitance benefit that such a structure provides. The inventive structure also results in higher uniaxial stress in the MOSFET channel compared to one which allows for a facet to grow at the trench isolation edge.

摘要翻译： 本发明提供了一种用于形成包括至少一个具有应力通道的pFET的CMOS结构的技术，其避免了现有技术中提到的问题。 具体地，本发明提供了一种避免在有源区和沟槽隔离区之间的界面处形成深峡谷的方法，而不需要沟槽隔离下拉，从而消除了硅化物对源/漏短路和接触问题的问题。 同时，本发明的方法提供了允许在间隔物边缘处形成小面的结构，保持了这种结构所提供的米勒电容有益效果。 与允许小面在沟槽隔离边缘生长的结构相比，本发明的结构还导致MOSFET沟道中更高的单轴应力。

公开(公告)号：US20070132038A1

公开(公告)日：2007-06-14

申请号：US11297522

申请日：2005-12-08

申请人： Yung Chong ,  Zhijiong Luo ,  Joo Kim ,  Brian Greene ,  Kern Rim

发明人： Yung Chong ,  Zhijiong Luo ,  Joo Kim ,  Brian Greene ,  Kern Rim

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.

摘要翻译： 示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫 门。 包括以下的示例性方法。 我们在衬底的第一区域上提供栅极结构。 栅极结构由栅极电介质，栅极和侧壁间隔物组成。 我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。 我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。 形成填充S / D凹槽的S / D应力区域。 与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。